entity ExampleDesign_Atlys is
  port (
    Atlys_SystemClock_100MHz   : in  STD_LOGIC;

    Atlys_GPIO_Button_Reset_n  : in  STD_LOGIC;
    Atlys_GPIO_Switches        : in  STD_LOGIC_VECTOR(7 downto 0);
    Atlys_GPIO_LED             : out STD_LOGIC_VECTOR(7 downto 0)
  );
end;

architecture rtl of ExampleDesign_Atlys is
  -- signal definitions ...
begin
  IBUF_GPIO_Button_Reset : IBUF
    port map (
      I => Atlys_GPIO_Button_Reset_n,
      O => GPIO_Button_Reset_n_IBUF
    );

  GPIO_Button_Reset_IBUF  <= not GPIO_Button_Reset_n_IBUF;

  -- more logic
end;

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
  single IOB component because the site type selected is not compatible.

  Further explanation:
  The component type is determined by the types of logic and the properties and
  configuration of the logic it contains. In this case an IO component of type
  IOB was chosen because the IO contains symbols and/or properties consistent
  with input, output, or bi-directional usage and contains no other symbols or
  properties that require a more specific IO component type. Please double
  check that the types of logic elements and all of their relevant properties
  and configuration options are compatible with the physical site type of the
  constraint.

Summary:
  Symbols involved:
    BUF symbol "IBUF_GPIO_Button_Reset" (Output Signal = GPIO_Button_Reset_IBUF)
    PAD symbol "Atlys_GPIO_Button_Reset_n" (Pad Signal =
  Atlys_GPIO_Button_Reset_n)
  Component type involved: IOB
  Site Location involved: