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  1. /*
  2.  * Copyright 2014 John Weber, Avnet Electronics Marketing
  3.  * Copyright 2013 Boundary Devices
  4.  * Copyright 2012 Freescale Semiconductor, Inc.
  5.  * Copyright 2011 Linaro Ltd.
  6.  *
  7.  * The code contained herein is licensed under the GNU General Public
  8.  * License. You may obtain a copy of the GNU General Public License
  9.  * Version 2 or later at the following locations:
  10.  *
  11.  * http://www.opensource.org/licenses/gpl-license.html
  12.  * http://www.gnu.org/copyleft/gpl.html
  13.  */
  14.  
  15. / {
  16.     aliases {
  17.         mxcfb0 = &mxcfb1;
  18.         mxcfb1 = &mxcfb2;
  19.         mxcfb2 = &mxcfb3;
  20.         mxcfb3 = &mxcfb4;
  21.     };
  22.  
  23.     memory {
  24.         reg = <0x10000000 0x40000000>;
  25.     };
  26.  
  27.     regulators {
  28.         compatible = "simple-bus";
  29.  
  30.         reg_1p8v: 1p8v {
  31.             compatible = "regulator-fixed";
  32.             regulator-name = "1P8V";
  33.             regulator-min-microvolt = <1800000>;
  34.             regulator-max-microvolt = <1800000>;
  35.             regulator-always-on;
  36.         };
  37.  
  38.         reg_2p5v: 2p5v {
  39.             compatible = "regulator-fixed";
  40.             regulator-name = "2P5V";
  41.             regulator-min-microvolt = <2500000>;
  42.             regulator-max-microvolt = <2500000>;
  43.             regulator-always-on;
  44.         };
  45.  
  46.         reg_3p3v: 3p3v {
  47.             compatible = "regulator-fixed";
  48.             regulator-name = "3P3V";
  49.             regulator-min-microvolt = <3300000>;
  50.             regulator-max-microvolt = <3300000>;
  51.             regulator-always-on;
  52.         };
  53.  
  54.         reg_usb_otg_vbus: usb_otg_vbus {
  55.             compatible = "regulator-fixed";
  56.             regulator-name = "usb_otg_vbus";
  57.             regulator-min-microvolt = <5000000>;
  58.             regulator-max-microvolt = <5000000>;
  59.             gpio = <&gpio1 1 GPIO_ACTIVE_LOW>;
  60.             enable-active-high;
  61.         };
  62.     };
  63.  
  64.     sound {
  65.         compatible = "fsl,imx6-wandboard-sgtl5000",
  66.                              "fsl,imx-audio-sgtl5000";
  67.         model = "imx6-wandboard-sgtl5000";
  68.         ssi-controller = <&ssi1>;
  69.         audio-codec = <&codec>;
  70.         audio-routing =
  71.             "MIC_IN", "Mic Jack",
  72.             "Mic Jack", "Mic Bias",
  73.             "Headphone Jack", "HP_OUT";
  74.         mux-int-port = <1>;
  75.         mux-ext-port = <3>;
  76.     };
  77.  
  78.         sound-spdif {
  79.                 compatible = "fsl,imx-audio-spdif";
  80.                 model = "imx-spdif";
  81.                 spdif-controller = <&spdif>;
  82.                 spdif-out;
  83.         };
  84.  
  85.     sound-hdmi {
  86.         compatible = "fsl,imx6q-audio-hdmi",
  87.                  "fsl,imx-audio-hdmi";
  88.         model = "imx-audio-hdmi";
  89.         hdmi-controller = <&hdmi_audio>;
  90.     };
  91.  
  92.         rfkill {
  93.                 compatible = "wand,imx6qdl-wandboard-rfkill";
  94.                 pinctrl-names = "default";
  95.                 pinctrl-0 = <>;
  96.  
  97.                 bluetooth-on = <&gpio3 13 0>;
  98.                 bluetooth-wake = <&gpio3 14 0>;
  99.                 bluetooth-host-wake = <&gpio3 15 0>;
  100.  
  101.                 wifi-ref-on = <&gpio2 29 0>;
  102.                 wifi-rst-n = <&gpio5 2 0>;
  103.                 wifi-reg-on = <&gpio1 26 0>;
  104.                 wifi-host-wake = <&gpio1 29 0>;
  105.                 wifi-wake = <&gpio1 30 0>;
  106.         };
  107.  
  108.   mxcfb1: fb@0 {
  109.         compatible = "fsl,mxc_sdc_fb";
  110.         disp_dev = "ldb";
  111.         interface_pix_fmt = "RGB666";
  112.         mode_str ="LDB-XGA";
  113.         default_bpp = <16>;
  114.         int_clk = <0>;
  115.         late_init = <0>;
  116.         status = "okay";
  117.     };
  118.  
  119.       mxcfb2: fb@1 {
  120.                 compatible = "fsl,mxc_sdc_fb";
  121.                 disp_dev = "ldb";
  122.                 interface_pix_fmt = "RGB666";
  123.                 mode_str ="LDB-XGA";
  124.                 default_bpp = <24>;
  125.                 int_clk = <0>;
  126.                 late_init = <0>;
  127.                 status = "okay";
  128.         };
  129.  
  130.     mxcfb3: fb@2 {
  131.         compatible = "fsl,mxc_sdc_fb";
  132.         disp_dev = "ldb";
  133.         interface_pix_fmt = "RGB666";
  134.         mode_str ="CLAA-WVGA";
  135.         default_bpp = <16>;
  136.         int_clk = <0>;
  137.         late_init = <0>;
  138.         status = "okay";
  139.     };
  140.  
  141.     mxcfb4: fb@3 {
  142.         compatible = "fsl,mxc_sdc_fb";
  143.         disp_dev = "ldb";
  144.         interface_pix_fmt = "RGB666";
  145.         mode_str ="LDB-XGA";
  146.         default_bpp = <16>;
  147.         int_clk = <0>;
  148.         late_init = <0>;
  149.         status = "okay";
  150.     };
  151. #if 0
  152.     lcd@0 {
  153.         compatible = "fsl,lcd";
  154.         ipu_id = <0>;
  155.         disp_id = <0>;
  156.         default_ifmt = "RGB565";
  157.         pinctrl-names = "default";
  158.         pinctrl-0 = <&pinctrl_ipu1_4>;
  159. #if 0
  160.         status = "okay";
  161. #endif
  162.     };
  163.  
  164.     backlight_lcd {
  165.         compatible = "pwm-backlight";
  166.         pwms = <&pwm1 0 5000000>;
  167.         brightness-levels = <0 4 8 16 32 64 128 255>;
  168.         default-brightness-level = <7>;
  169.     };
  170.  
  171.     backlight_lvds {
  172.         compatible = "pwm-backlight";
  173.         pwms = <&pwm4 0 5000000>;
  174.         brightness-levels = <0 4 8 16 32 64 128 255>;
  175.         default-brightness-level = <7>;
  176.     };
  177. #endif
  178.     v4l2_cap_0 {
  179.         compatible = "fsl,imx6q-v4l2-capture";
  180.         ipu_id = <0>;
  181.         csi_id = <0>;
  182.         mclk_source = <0>;
  183.         status = "okay";
  184.     };
  185.  
  186.     v4l2_out {
  187.         compatible = "fsl,mxc_v4l2_output";
  188.         status = "okay";
  189.     };
  190.  
  191. };
  192.  
  193.  
  194. &audmux {
  195.     pinctrl-names = "default";
  196.     pinctrl-0 = <&pinctrl_audmux_2>;
  197.     status = "okay";
  198. };
  199.  
  200.  
  201. &fec {
  202.     pinctrl-names = "default";
  203.     pinctrl-0 = <&pinctrl_enet_3>;
  204.     phy-mode = "rgmii";
  205.     status = "okay";
  206. };
  207.  
  208. &hdmi_audio {
  209.     status = "okay";
  210. };
  211.  
  212. &hdmi_core {
  213.     ipu_id = <0>;
  214.     disp_id = <0>;
  215.     status = "okay";
  216. };
  217.  
  218. &hdmi_video {
  219.     fsl,phy_reg_vlev = <0x0294>;
  220.     fsl,phy_reg_cksymtx = <0x800d>;
  221.     status = "okay";
  222. };
  223.  
  224. &i2c1 {
  225.     clock-frequency = <100000>;
  226.     pinctrl-names = "default";
  227.     pinctrl-0 = <&pinctrl_i2c1_1>;
  228.     status = "okay";
  229.  
  230.     hdmi: edid@50 {
  231.         compatible = "fsl,imx6-hdmi-i2c";
  232.         reg = <0x50>;
  233.     };
  234.  
  235. };
  236.  
  237. &i2c2 {
  238.     clock-frequency = <100000>;
  239.     pinctrl-names = "default";
  240.     pinctrl-0 = <&pinctrl_i2c2_2>;
  241.     status = "okay";
  242.  
  243.     ov5640_mipi: ov5640_mipi@3c {
  244.         compatible = "ovti,ov5640_mipi";
  245.         reg = <0x3c>;
  246.         clocks = <&clks 200>;
  247.         clock-names = "csi_mclk";
  248.         DOVDD-supply = <&reg_1p8v>;
  249.         AVDD-supply = <&reg_2p5v>;
  250.         DVDD-supply = <&reg_1p8v>;
  251.         pwn-gpios = <&gpio1 6 1>;
  252.         rst-gpios = <&gpio4 14 0>;
  253.         ipu_id = <0>;
  254.         csi_id = <0>;
  255.         mclk = <24000000>;
  256.         mclk_source = <0>;
  257.     };
  258.  
  259.     codec: sgtl5000@0a {
  260.         compatible = "fsl,sgtl5000";
  261.         reg = <0x0a>;
  262.         clocks = <&clks 201>;
  263.         VDDA-supply = <&reg_2p5v>;
  264.         VDDIO-supply = <&reg_3p3v>;
  265.     };
  266. };
  267.  
  268. &i2c3 {
  269.         clock-frequency = <100000>;
  270.         pinctrl-names = "default";
  271.         pinctrl-0 = <&pinctrl_i2c3_3>;
  272.         status = "okay";
  273. };
  274.  
  275. /*
  276. For reference here, the PAD_CTL bitfield definition from
  277. Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
  278.  
  279. CONFIG bits definition:
  280. PAD_CTL_HYS                     (1 << 16)
  281. PAD_CTL_PUS_100K_DOWN           (0 << 14)
  282. PAD_CTL_PUS_47K_UP              (1 << 14)
  283. PAD_CTL_PUS_100K_UP             (2 << 14)
  284. PAD_CTL_PUS_22K_UP              (3 << 14)
  285. PAD_CTL_PUE                     (1 << 13)
  286. PAD_CTL_PKE                     (1 << 12)
  287. PAD_CTL_ODE                     (1 << 11)
  288. PAD_CTL_SPEED_LOW               (1 << 6)
  289. PAD_CTL_SPEED_MED               (2 << 6)
  290. PAD_CTL_SPEED_HIGH              (3 << 6)
  291. PAD_CTL_DSE_DISABLE             (0 << 3)
  292. PAD_CTL_DSE_240ohm              (1 << 3)
  293. PAD_CTL_DSE_120ohm              (2 << 3)
  294. PAD_CTL_DSE_80ohm               (3 << 3)
  295. PAD_CTL_DSE_60ohm               (4 << 3)
  296. PAD_CTL_DSE_48ohm               (5 << 3)
  297. PAD_CTL_DSE_40ohm               (6 << 3)
  298. PAD_CTL_DSE_34ohm               (7 << 3)
  299. PAD_CTL_SRE_FAST                (1 << 0)
  300. PAD_CTL_SRE_SLOW                (0 << 0)
  301.  
  302. Example, the Control Pad Setting
  303.  
  304.     0x0f0b0
  305.  
  306. corresponds to:
  307.  
  308.    0b1111000010110000
  309.  
  310. which is:
  311.  
  312.    PAD_CTL_PUS_22K_UP | PAD_CTL_PUE | PAD_CTL_PKE |
  313.    PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm
  314.  
  315. For more information about this, refer to the IOMUXC section of the i.MX6
  316. reference manual.
  317.  
  318. */
  319.  
  320. &iomuxc {
  321.     pinctrl-names = "default";
  322.     pinctrl-0 = <&pinctrl_hog_1>;
  323.  
  324.     imx6qdl-wandboard {
  325.         pinctrl_hog_1: hoggrp-1 {
  326.             fsl,pins = <
  327.                 MX6QDL_PAD_GPIO_0__CCM_CLKO1        0x130b0
  328.                 MX6QDL_PAD_EIM_D22__GPIO3_IO22      0x80000000  /* USB Power Enable */
  329.                 MX6QDL_PAD_GPIO_2__GPIO1_IO02       0x80000000  /* USDHC1 CD */
  330.                 MX6QDL_PAD_EIM_DA9__GPIO3_IO09      0x80000000  /* uSDHC3 CD */
  331.                 MX6QDL_PAD_GPIO_0__CCM_CLKO1        0x000b0     /* SGTL5000 sys_mclk */
  332.                 MX6QDL_PAD_GPIO_6__GPIO1_IO06       0x0b0b0     /* ov5640 mipi powerdown */
  333.                 MX6QDL_PAD_KEY_COL4__GPIO4_IO14     0x000b0     /* ov5640 mipi reset */
  334.                 MX6QDL_PAD_GPIO_3__CCM_CLKO2        0x000b0     /* ov5640 mclk */
  335.                 MX6QDL_PAD_EIM_A25__GPIO5_IO02      0x0f0b0     /* WIFI_ON (reset, active low) */
  336.                 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26    0x000b0     /* WL_REG_ON (unused) */
  337.                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29    0x80000000  /* WL_HOST_WAKE, input */
  338.                 MX6QDL_PAD_EIM_EB1__GPIO2_IO29      0x0f0b0     /* EIM_EB1 (Wifi Power Enable) */
  339.                 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30    0x80000000  /* WL_WAKE (unused) */
  340.                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29      0x80000000
  341.                                 MX6QDL_PAD_EIM_DA13__GPIO3_IO13     0x80000000  /* BT_ON */
  342.                                 MX6QDL_PAD_EIM_DA14__GPIO3_IO14     0x80000000  /* BT_WAKE */
  343.                                 MX6QDL_PAD_EIM_DA15__GPIO3_IO15     0x80000000  /* BT_HOST_WAKE */
  344.             >;
  345.         };
  346.  
  347.             pinctrl_spdif_wand: spdifgrp {
  348.                     fsl,pins = <
  349.                 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT                 0x1b0b0
  350.             >;
  351.             };
  352.     };
  353.     gpio {
  354.         pinctrl_gpio: gpiogrp {
  355.             fsl,pins = <
  356.                                 MX6QDL_PAD_EIM_DA12__GPIO3_IO12   0x80000000 /* GPIO3_12 EDM pin 255 */
  357.                                 MX6QDL_PAD_EIM_DA11__GPIO3_IO11   0x80000000 /* GPIO3_11 EDM pin 256 */
  358.                                 MX6QDL_PAD_EIM_DA10__GPIO3_IO10   0x80000000 /* GPIO3_10 EDM pin 257 */
  359.                                 MX6QDL_PAD_EIM_D27__GPIO3_IO27    0x80000000 /* GPIO3_27 EDM pin 258 */
  360.                                 MX6QDL_PAD_EIM_D26__GPIO3_IO26    0x80000000 /* GPIO3_26 EDM pin 259 */
  361.                                 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31   0x80000000 /* GPIO6_31 EDM pin 260 */
  362.                                 MX6QDL_PAD_EIM_DA8__GPIO3_IO08    0x80000000 /* GPIO3_8  EDM pin 261 */
  363.                                 MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x80000000 /* GPIO1_24 EDM pin 262 */
  364.                                 MX6QDL_PAD_GPIO_19__GPIO4_IO05    0x80000000 /* GPIO4_5  EDM pin 263 */
  365.                                 MX6QDL_PAD_SD3_RST__GPIO7_IO08    0x80000000 /* GPIO7_8  EDM pin 264 */
  366.             >;
  367.         };
  368.     };
  369. };
  370.  
  371. &ldb {
  372.     status = "okay";
  373.  
  374.     lvds-channel@0 {
  375.         fsl,data-mapping = "spwg";
  376.         fsl,data-width = <18>;
  377.         status = "okay";
  378.  
  379.         display-timings {
  380.             native-mode = <&timing0>;
  381.             timing0: hsd100pxn1 {
  382.                 clock-frequency = <65000000>;
  383.                 hactive = <1024>;
  384.                 vactive = <768>;
  385.                 hback-porch = <220>;
  386.                 hfront-porch = <40>;
  387.                 vback-porch = <21>;
  388.                 vfront-porch = <7>;
  389.                 hsync-len = <60>;
  390.                 vsync-len = <10>;
  391.             };
  392.         };
  393.     };
  394. };
  395.  
  396. #if 0
  397. &ldb {
  398.     ipu_id = <0>;
  399.     disp_id = <1>;
  400.     ext_ref = <1>;
  401.     mode = "sin0";
  402.     sec_ipu_id = <1>;
  403.     sec_disp_id = <1>;
  404.     status = "okay";
  405. };
  406. #endif
  407.  
  408. &mipi_csi {
  409.     ipu_id = <0>;
  410.     csi_id = <0>;
  411.     v_channel = <0>;
  412.     lanes = <2>;
  413.     status = "okay";
  414. };
  415.  
  416. &pcie {
  417.     status = "okay";
  418. };
  419.  
  420. #if 0
  421. &pwm1 {
  422.     pinctrl-names = "default";
  423.     pinctrl-0 = <&pinctrl_pwm1_1>;
  424.     status = "okay";
  425. };
  426.  
  427. &pwm3 {
  428.     pinctrl-names = "default";
  429.     pinctrl-0 = <&pinctrl_pwm3_2>;
  430.     status = "okay";
  431. };
  432.  
  433. &pwm4 {
  434.     pinctrl-names = "default";
  435.     pinctrl-0 = <&pinctrl_pwm4_2>;
  436.     status = "okay";
  437. };
  438. #endif
  439.  
  440. &spdif {
  441.         pinctrl-names = "default";
  442.         pinctrl-0 = <&pinctrl_spdif_wand>;
  443.         status = "okay";
  444. };
  445.  
  446. &ssi1 {
  447.     fsl,mode = "i2s-slave";
  448.     status = "okay";
  449. };
  450.  
  451. &uart1 {
  452.     pinctrl-names = "default";
  453.     pinctrl-0 = <&pinctrl_uart1_1>;
  454.     status = "okay";
  455. };
  456.  
  457. &uart3 {
  458.         pinctrl-names = "default";
  459.         pinctrl-0 = <&pinctrl_uart3_1>;
  460.         fsl,uart-has-rtscts;
  461.         status = "okay";
  462. };
  463.  
  464. &usbh1 {
  465.     status = "okay";
  466. };
  467.  
  468. &usbotg {
  469.     vbus-supply = <&reg_usb_otg_vbus>;
  470.     pinctrl-names = "default";
  471.     pinctrl-0 = <&pinctrl_usbotg_1>;
  472.     disable-over-current;
  473.     dr_mode = "peripheral";
  474.     status = "okay";
  475. };
  476.  
  477. &usdhc1 {  /* Baseboard microSD slot */
  478.     pinctrl-names = "default";
  479.     pinctrl-0 = <&pinctrl_usdhc1_1>;
  480.     bus-width = <4>;
  481.     vmmc-supply = <&reg_3p3v>;
  482.     cd-gpios = <&gpio1 2 0>;
  483.     status = "okay";
  484. };
  485.  
  486. &usdhc2 {  /* Broadcom Wifi/BT  */
  487.     pinctrl-names = "default";
  488.     pinctrl-0 = <&pinctrl_usdhc2_2>;
  489.     bus-width = <4>;
  490.     //non-removable;
  491.     vmmc-supply = <&reg_3p3v>;
  492.     keep-power-in-suspend;
  493.     status = "okay";
  494. };
  495.  
  496. &usdhc3 { /* Module microSD slot */
  497.     pinctrl-names = "default";
  498.     pinctrl-0 = <&pinctrl_usdhc3_2>;
  499.     vmmc-supply = <&reg_3p3v>;
  500.         cd-gpios = <&gpio3 9 0>;
  501.     status = "okay";
  502. };
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