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By: a guest on Apr 15th, 2013  |  syntax: VeriLog  |  size: 0.55 KB  |  views: 33  |  expires: Never
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  1. // Old behaviour
  2. /* Machine-generated using Migen */
  3. module top(
  4.  
  5. );
  6.  
  7. reg [127:0] d;
  8. wire [15:0] q;
  9.  
  10. // synthesis translate off
  11. reg dummy_s;
  12. initial dummy_s <= 1'd0;
  13. // synthesis translate on
  14. assign q = d[64:1][32:1][16:1];
  15.  
  16. initial begin
  17.         d <= 1'd0;
  18. end
  19.  
  20. endmodule
  21.  
  22. // New behaviour
  23. /* Machine-generated using Migen */
  24. module top(
  25.  
  26. );
  27.  
  28. reg [127:0] d;
  29. wire [15:0] q;
  30.  
  31. // synthesis translate off
  32. reg dummy_s;
  33. initial dummy_s <= 1'd0;
  34. // synthesis translate on
  35. assign q = d[18:3];
  36.  
  37. initial begin
  38.         d <= 1'd0;
  39. end
  40.  
  41. endmodule
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