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Jan 31st, 2014
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VHDL 0.86 KB | None | 0 0
  1. ----------------
  2.     -- hivek_core --
  3.     ----------------
  4.     type hivek_path_in_t is record
  5.         dcache_data : std_logic_vector(31 downto 0);
  6.     end record;
  7.  
  8.     type hivek_path_out_t is record
  9.         dcache_wren : std_logic;
  10.         dcache_addr : std_logic_vector(31 downto 0);
  11.         dcache_data : std_logic_vector(31 downto 0);
  12.     end record;
  13.  
  14.     type hivek_in_t is record
  15.         icache_data : std_logic_vector(63 downto 0);
  16.         op0 : hivek_path_in_t;
  17.         op1 : hivek_path_in_t;
  18.     end record;
  19.  
  20.     type hivek_out_t is record
  21.         icache_addr : std_logic_vector(31 downto 0);
  22.         op0 : hivek_path_out_t;
  23.         op1 : hivek_path_out_t;
  24.     end record;
  25.  
  26. entity hivek is
  27.     port (
  28.         clock : in std_logic;
  29.         reset : in std_logic;
  30.         din : in hivek_in_t;
  31.         dout : out hivek_out_t
  32.     );
  33. end hivek;
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