From ee3cafb3dba1b98ff12a5add86cb2e3a50d2045e Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 28 Feb 2015 20:07:23 +0100
Subject: [PATCH] vivado patch

---
 misoclib/soc/sdram.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index c853432..e5f5e44 100644
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -1,5 +1,6 @@
 from migen.fhdl.std import *
 from migen.bus import wishbone, csr
+from migen.fhdl.simplify import FullMemoryWE

 from misoclib.mem.sdram.bus import dfi, lasmibus, wishbone2lasmi
 from misoclib.mem.sdram import minicon, lasmicon
@@ -54,7 +55,7 @@ class SDRAMSoC(SoC):
 				self.submodules.memtest_r = memtest.MemtestReader(self.lasmixbar.get_master())

 			if self.with_l2:
-				self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master())
+				self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master()))
 				sdram_size = 2**self.lasmicon.lasmic.aw*self.lasmicon.lasmic.dw*self.lasmicon.lasmic.nbanks//8
 				self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, sdram_size)

--
1.9.2.msysgit.0