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lpc1766 - led on

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Mar 2nd, 2010
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  1.  
  2. helloworld.elf: file format elf32-littlearm
  3.  
  4.  
  5. Disassembly of section .text:
  6.  
  7. 00000000 <__cs3_interrupt_vector>:
  8. 0: 10008000 andne r8, r0, r0
  9. 4: 000000cc andeq r0, r0, ip, asr #1
  10. 8: 000000e8 andeq r0, r0, r8, ror #1
  11. c: 000000ea andeq r0, r0, sl, ror #1
  12. 10: 000000ec andeq r0, r0, ip, ror #1
  13. 14: 000000ee andeq r0, r0, lr, ror #1
  14. 18: 000000f0 strdeq r0, [r0], -r0
  15. ...
  16. 2c: 000000f2 strdeq r0, [r0], -r2
  17. 30: 000000f4 strdeq r0, [r0], -r4
  18. 34: 00000000 andeq r0, r0, r0
  19. 38: 000000f6 strdeq r0, [r0], -r6
  20. 3c: 000000f8 strdeq r0, [r0], -r8
  21. 40: 000000fa strdeq r0, [r0], -sl
  22. 44: 000000fa strdeq r0, [r0], -sl
  23. 48: 000000fa strdeq r0, [r0], -sl
  24. 4c: 000000fa strdeq r0, [r0], -sl
  25. 50: 000000fa strdeq r0, [r0], -sl
  26. 54: 000000fa strdeq r0, [r0], -sl
  27. 58: 000000fa strdeq r0, [r0], -sl
  28. 5c: 000000fa strdeq r0, [r0], -sl
  29. 60: 000000fa strdeq r0, [r0], -sl
  30. 64: 000000fa strdeq r0, [r0], -sl
  31. 68: 000000fa strdeq r0, [r0], -sl
  32. 6c: 000000fa strdeq r0, [r0], -sl
  33. 70: 000000fa strdeq r0, [r0], -sl
  34. 74: 000000fa strdeq r0, [r0], -sl
  35. 78: 000000fa strdeq r0, [r0], -sl
  36. 7c: 000000fa strdeq r0, [r0], -sl
  37. 80: 000000fa strdeq r0, [r0], -sl
  38. 84: 000000fa strdeq r0, [r0], -sl
  39. 88: 000000fa strdeq r0, [r0], -sl
  40. 8c: 000000fa strdeq r0, [r0], -sl
  41. 90: 000000fa strdeq r0, [r0], -sl
  42. 94: 000000fa strdeq r0, [r0], -sl
  43. 98: 000000fa strdeq r0, [r0], -sl
  44. 9c: 000000fa strdeq r0, [r0], -sl
  45. a0: 000000fa strdeq r0, [r0], -sl
  46. a4: 000000fa strdeq r0, [r0], -sl
  47. a8: 000000fa strdeq r0, [r0], -sl
  48. ac: 000000fa strdeq r0, [r0], -sl
  49. b0: 000000fa strdeq r0, [r0], -sl
  50. b4: 000000fa strdeq r0, [r0], -sl
  51. b8: 000000fa strdeq r0, [r0], -sl
  52. bc: 000000fa strdeq r0, [r0], -sl
  53. c0: 000000fa strdeq r0, [r0], -sl
  54. c4: 000000fa strdeq r0, [r0], -sl
  55. c8: 000000fa strdeq r0, [r0], -sl
  56.  
  57. 000000cc <__cs3_reset_cortex_m>:
  58. cc: 4800 ldr r0, [pc, #0] ; (d0 <__cs3_reset_cortex_m+0x4>)
  59. ce: 4700 bx r0
  60. d0: 000000d5 ldrdeq r0, [r0], -r5
  61.  
  62. 000000d4 <main>:
  63. d4: b480 push {r7}
  64. d6: af00 add r7, sp, #0
  65. d8: f24c 0323 movw r3, #49187 ; 0xc023
  66. dc: f2c2 0309 movt r3, #8201 ; 0x2009
  67. e0: f04f 0202 mov.w r2, #2
  68. e4: 601a str r2, [r3, #0]
  69. e6: e7fe b.n e6 <main+0x12>
  70.  
  71. 000000e8 <NMI_Handler>:
  72. e8: e7fe b.n e8 <NMI_Handler>
  73.  
  74. 000000ea <HardFault_Handler>:
  75. ea: e7fe b.n ea <HardFault_Handler>
  76.  
  77. 000000ec <MemManage_Handler>:
  78. ec: e7fe b.n ec <MemManage_Handler>
  79.  
  80. 000000ee <BusFault_Handler>:
  81. ee: e7fe b.n ee <BusFault_Handler>
  82.  
  83. 000000f0 <UsageFault_Handler>:
  84. f0: e7fe b.n f0 <UsageFault_Handler>
  85.  
  86. 000000f2 <SVC_Handler>:
  87. f2: e7fe b.n f2 <SVC_Handler>
  88.  
  89. 000000f4 <DebugMon_Handler>:
  90. f4: e7fe b.n f4 <DebugMon_Handler>
  91.  
  92. 000000f6 <PendSV_Handler>:
  93. f6: e7fe b.n f6 <PendSV_Handler>
  94.  
  95. 000000f8 <SysTick_Handler>:
  96. f8: e7fe b.n f8 <SysTick_Handler>
  97.  
  98. 000000fa <Default_Handler>:
  99. fa: e7fe b.n fa <Default_Handler>
  100.  
  101. 000000fc <__cs3_regions>:
  102. fc: 0000 lsls r0, r0, #0
  103. fe: 0000 lsls r0, r0, #0
  104. 100: 0118 lsls r0, r3, #4
  105. 102: 0000 lsls r0, r0, #0
  106. 104: 0000 lsls r0, r0, #0
  107. 106: 1000 asrs r0, r0, #32
  108. ...
  109.  
  110. Disassembly of section .ARM.exidx:
  111.  
  112. 00000110 <_etext-0x8>:
  113. 110: 7fffffbc svcvc 0x00ffffbc
  114. 114: 00000001 andeq r0, r0, r1
  115.  
  116. Disassembly of section .heap:
  117.  
  118. 10000000 <__cs3_heap_start>:
  119. ...
  120.  
  121. Disassembly of section .stack:
  122.  
  123. 10007f00 <__cs3_stack_mem>:
  124. ...
  125.  
  126. Disassembly of section .ARM.attributes:
  127.  
  128. 00000000 <.ARM.attributes>:
  129. 0: 00000f41 andeq r0, r0, r1, asr #30
  130. 4: 61656100 cmnvs r5, r0, lsl #2
  131. 8: 01006962 tsteq r0, r2, ror #18
  132. c: 00000005 andeq r0, r0, r5
  133.  
  134. Disassembly of section .comment:
  135.  
  136. 00000000 <.comment>:
  137. 0: 3a434347 bcc 10d0d24 <__cs3_region_size_rom+0x1090d24>
  138. 4: 4e472820 cdpmi 8, 4, cr2, cr7, cr0, {1}
  139. 8: 34202955 strtcc r2, [r0], #-2389 ; 0x955
  140. c: 322e342e eorcc r3, lr, #771751936 ; 0x2e000000
  141. ...
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