stm32f4 pwm and timer interrupt

void TIM2_IRQHandler(void)
{
    if (TIM_GetITStatus(TIM2, TIM_IT_Update) != RESET)
        {
            TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
            ++global_interruptcount;
        }
}

TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
TIM_OCInitTypeDef  TIM_OCInitStructure;

uint32_t CCR1_Val = 12000000;
uint32_t PrescalerValue = 0;

/**
  * @brief  Configure the TIM4 Ouput Channels.
  * @param  None
  * @retval None
  */
void TIM_Config1(void)
{
    GPIO_InitTypeDef GPIO_InitStructure;

    /* TIM4 clock enable */
    RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);

    /* GPIOA clock enable */
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);

    /* GPIOD Configuration: TIM2 CH1 (PA5) */
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;// | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ;
    GPIO_Init(GPIOA, &GPIO_InitStructure);

    /* Connect TIM2 pins to AF2 */
    GPIO_PinAFConfig(GPIOA, GPIO_PinSource5, GPIO_AF_TIM2);
}

void TIM_Config2(){

    NVIC_InitTypeDef NVIC_InitStructure;

    NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
    NVIC_Init(&NVIC_InitStructure);

    /* -----------------------------------------------------------------------
        TIM4 Configuration: generate 4 PWM signals with 4 different duty cycles.

        In this example TIM4 input clock (TIM4CLK) is set to 4 * APB1 clock (PCLK1),
        since TIMPRE bit from RCC_DCKCFGR register is set.
          TIM4CLK = 4 * PCLK1
          PCLK1 = HCLK / 4
          => TIM4CLK = HCLK = SystemCoreClock

        To get TIM4 counter clock at 21 MHz, the prescaler is computed as follows:
           Prescaler = (TIM4CLK / TIM4 counter clock) - 1
           Prescaler = (SystemCoreClock /21 MHz) - 1

        To get TIM4 output clock at 30 KHz, the period (ARR)) is computed as follows:
           ARR = (TIM4 counter clock / TIM4 output clock) - 1
               = 699

        TIM4 Channel1 duty cycle = (TIM4_CCR1/ TIM4_ARR)* 100 = 50%
        TIM4 Channel2 duty cycle = (TIM4_CCR2/ TIM4_ARR)* 100 = 37.5%
        TIM4 Channel3 duty cycle = (TIM4_CCR3/ TIM4_ARR)* 100 = 25%
        TIM4 Channel4 duty cycle = (TIM4_CCR4/ TIM4_ARR)* 100 = 12.5%

        Note:
         SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f4xx.c file.
         Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate()
         function to update SystemCoreClock variable value. Otherwise, any configuration
         based on this variable will be incorrect.
      ----------------------------------------------------------------------- */
      RCC_TIMCLKPresConfig(RCC_TIMPrescActivated);

      /* Compute the prescaler value */
      PrescalerValue = (uint32_t) (SystemCoreClock / 21000000) - 1;
      //PrescalerValue = (uint32_t) (SystemCoreClock / 10) - 1;


      /* Time base configuration */
      TIM_TimeBaseStructure.TIM_Period = 21000000/100-1;
      TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
      TIM_TimeBaseStructure.TIM_ClockDivision = 0;
      TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;

      TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);

      /* PWM1 Mode configuration: Channel1 */
      TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
      TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
      TIM_OCInitStructure.TIM_Pulse = CCR1_Val/100;
      TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;

      TIM_OC1Init(TIM2, &TIM_OCInitStructure);

      TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Enable);

      //---

      TIM_ARRPreloadConfig(TIM2, ENABLE);

      TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);

      /* TIM2 enable counter */
      TIM_Cmd(TIM2, ENABLE);
}