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-- Company:
-- Engineer:
--
-- Create Date:    19:42:04 02/27/2017
-- Design Name:
-- Module Name:    resultArray - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity resultArray is
Port ( clk : in  STD_LOGIC;
		 inputres : in STD_LOGIC_VECTOR (15 downto 0);
		 inputaddres: in STD_LOGIC_VECTOR (2 downto 0);
		 selectedres :out STD_LOGIC_VECTOR (15 downto 0));
end resultArray;

architecture Structural of resultArray is
type resArray is array ( 7 downto 0) of STD_LOGIC_VECTOR(15 downto 0);
signal input : resArray;
signal output : STD_LOGIC_VECTOR (15 downto 0) :="0000000000000000" ;
  begin

   process (clk)
    variable x : integer range 0 to 7 :=0;
	 variable z: integer range 0 to 7 :=0;

    begin
	  if (clk'event and clk = '1' and x >0) then
	  z:= x-1;
	  input(z) <= inputres;
	  end if;
	  if (x<9) then
	  x := x+1;
	  end if;
   end process;

	--process(inputaddres)
	--variable y : integer range 0 to 7 :=0;
	--begin
	--y:= 0;
	--if ( inputaddres(0)='1') then
	--y:= 1;
	--end if;
	--end process;
 end Structural;