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  1. proc getPresetInfo {} {
  2. return [dict create name {Zybo_Base} description {Zybo_Base} vlnv xilinx.com:ip:processing_system7:5.5 display_name {Zybo_Base} ]
  3. }
  4.  
  5. proc validate_preset {IPINST} { return true }
  6.  
  7.  
  8. proc apply_preset {IPINST} {
  9. return [dict create \
  10. CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
  11. CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
  12. CONFIG.PCW_UART0_BASEADDR {0xE0000000} \
  13. CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \
  14. CONFIG.PCW_UART1_BASEADDR {0xE0001000} \
  15. CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \
  16. CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \
  17. CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \
  18. CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \
  19. CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \
  20. CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \
  21. CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \
  22. CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \
  23. CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \
  24. CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \
  25. CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \
  26. CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \
  27. CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \
  28. CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \
  29. CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \
  30. CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \
  31. CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \
  32. CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \
  33. CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \
  34. CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \
  35. CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \
  36. CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \
  37. CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \
  38. CONFIG.PCW_USB0_BASEADDR {0xE0102000} \
  39. CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \
  40. CONFIG.PCW_USB1_BASEADDR {0xE0103000} \
  41. CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \
  42. CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \
  43. CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \
  44. CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \
  45. CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \
  46. CONFIG.PCW_FCLK_CLK0_BUF {true} \
  47. CONFIG.PCW_FCLK_CLK1_BUF {true} \
  48. CONFIG.PCW_FCLK_CLK2_BUF {true} \
  49. CONFIG.PCW_FCLK_CLK3_BUF {false} \
  50. CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525.000000} \
  51. CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
  52. CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {14} \
  53. CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
  54. CONFIG.PCW_UIPARAM_DDR_CL {7} \
  55. CONFIG.PCW_UIPARAM_DDR_CWL {6} \
  56. CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
  57. CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
  58. CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
  59. CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
  60. CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
  61. CONFIG.PCW_UIPARAM_DDR_AL {0} \
  62. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.073} \
  63. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.034} \
  64. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.03} \
  65. CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.082} \
  66. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.176} \
  67. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.159} \
  68. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.162} \
  69. CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.187} \
  70. CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {27.85} \
  71. CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {22.87} \
  72. CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {22.9} \
  73. CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {29.9} \
  74. CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {27} \
  75. CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {22.8} \
  76. CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {24} \
  77. CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {30.45} \
  78. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {20.6} \
  79. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {20.6} \
  80. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {20.6} \
  81. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {20.6} \
  82. CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {101.239} \
  83. CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {79.5025} \
  84. CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {60.536} \
  85. CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {71.7715} \
  86. CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {104.5365} \
  87. CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {70.676} \
  88. CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {59.1615} \
  89. CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {81.319} \
  90. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {54.563} \
  91. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {54.563} \
  92. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {54.563} \
  93. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {54.563} \
  94. CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {180} \
  95. CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {180} \
  96. CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {180} \
  97. CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {180} \
  98. CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {180} \
  99. CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {180} \
  100. CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {180} \
  101. CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {180} \
  102. CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {165} \
  103. CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {165} \
  104. CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {165} \
  105. CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {165} \
  106. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.073} \
  107. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.034} \
  108. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.030} \
  109. CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.082} \
  110. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.176} \
  111. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.159} \
  112. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.162} \
  113. CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.187} \
  114. CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
  115. CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50.000000} \
  116. CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650.000000} \
  117. CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
  118. CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
  119. CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
  120. CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
  121. CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \
  122. CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
  123. CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {50} \
  124. CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
  125. CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
  126. CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \
  127. CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \
  128. CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {108.333336} \
  129. CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \
  130. CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
  131. CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
  132. CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
  133. CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
  134. CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
  135. CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
  136. CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
  137. CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
  138. CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
  139. CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
  140. CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {150} \
  141. CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {12.288} \
  142. CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {100.000000} \
  143. CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \
  144. CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \
  145. CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \
  146. CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
  147. CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
  148. CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
  149. CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
  150. CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \
  151. CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \
  152. CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \
  153. CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {50.000000} \
  154. CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
  155. CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
  156. CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \
  157. CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \
  158. CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \
  159. CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \
  160. CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \
  161. CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
  162. CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
  163. CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
  164. CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {150.000000} \
  165. CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {12.264151} \
  166. CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {100.000000} \
  167. CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
  168. CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
  169. CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
  170. CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
  171. CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
  172. CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
  173. CONFIG.PCW_CLK0_FREQ {100000000} \
  174. CONFIG.PCW_CLK1_FREQ {150000000} \
  175. CONFIG.PCW_CLK2_FREQ {12264151} \
  176. CONFIG.PCW_CLK3_FREQ {100000000} \
  177. CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
  178. CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
  179. CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
  180. CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
  181. CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
  182. CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \
  183. CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {20} \
  184. CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
  185. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
  186. CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
  187. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {10} \
  188. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {7} \
  189. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {53} \
  190. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {10} \
  191. CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {1} \
  192. CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
  193. CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {2} \
  194. CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
  195. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
  196. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
  197. CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
  198. CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
  199. CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
  200. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \
  201. CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \
  202. CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
  203. CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \
  204. CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \
  205. CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \
  206. CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \
  207. CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \
  208. CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \
  209. CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \
  210. CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \
  211. CONFIG.PCW_IOPLL_CTRL_FBDIV {20} \
  212. CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \
  213. CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \
  214. CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
  215. CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \
  216. CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \
  217. CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
  218. CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \
  219. CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \
  220. CONFIG.PCW_EN_EMIO_CAN0 {0} \
  221. CONFIG.PCW_EN_EMIO_CAN1 {0} \
  222. CONFIG.PCW_EN_EMIO_ENET0 {0} \
  223. CONFIG.PCW_EN_EMIO_ENET1 {0} \
  224. CONFIG.PCW_EN_EMIO_GPIO {0} \
  225. CONFIG.PCW_EN_EMIO_I2C0 {1} \
  226. CONFIG.PCW_EN_EMIO_I2C1 {0} \
  227. CONFIG.PCW_EN_EMIO_PJTAG {0} \
  228. CONFIG.PCW_EN_EMIO_SDIO0 {0} \
  229. CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
  230. CONFIG.PCW_EN_EMIO_WP_SDIO0 {1} \
  231. CONFIG.PCW_EN_EMIO_SDIO1 {0} \
  232. CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
  233. CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
  234. CONFIG.PCW_EN_EMIO_SPI0 {0} \
  235. CONFIG.PCW_EN_EMIO_SPI1 {0} \
  236. CONFIG.PCW_EN_EMIO_UART0 {0} \
  237. CONFIG.PCW_EN_EMIO_UART1 {0} \
  238. CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
  239. CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \
  240. CONFIG.PCW_EN_EMIO_TTC0 {0} \
  241. CONFIG.PCW_EN_EMIO_TTC1 {0} \
  242. CONFIG.PCW_EN_EMIO_WDT {0} \
  243. CONFIG.PCW_EN_EMIO_TRACE {0} \
  244. CONFIG.PCW_USE_M_AXI_GP0 {1} \
  245. CONFIG.PCW_USE_M_AXI_GP1 {0} \
  246. CONFIG.PCW_USE_S_AXI_GP0 {0} \
  247. CONFIG.PCW_USE_S_AXI_GP1 {0} \
  248. CONFIG.PCW_USE_S_AXI_ACP {0} \
  249. CONFIG.PCW_USE_S_AXI_HP0 {1} \
  250. CONFIG.PCW_USE_S_AXI_HP1 {0} \
  251. CONFIG.PCW_USE_S_AXI_HP2 {0} \
  252. CONFIG.PCW_USE_S_AXI_HP3 {0} \
  253. CONFIG.PCW_M_AXI_GP0_FREQMHZ {100} \
  254. CONFIG.PCW_M_AXI_GP1_FREQMHZ {10} \
  255. CONFIG.PCW_S_AXI_GP0_FREQMHZ {10} \
  256. CONFIG.PCW_S_AXI_GP1_FREQMHZ {10} \
  257. CONFIG.PCW_S_AXI_ACP_FREQMHZ {10} \
  258. CONFIG.PCW_S_AXI_HP0_FREQMHZ {150} \
  259. CONFIG.PCW_S_AXI_HP1_FREQMHZ {100} \
  260. CONFIG.PCW_S_AXI_HP2_FREQMHZ {10} \
  261. CONFIG.PCW_S_AXI_HP3_FREQMHZ {10} \
  262. CONFIG.PCW_USE_DMA0 {1} \
  263. CONFIG.PCW_USE_DMA1 {1} \
  264. CONFIG.PCW_USE_DMA2 {0} \
  265. CONFIG.PCW_USE_DMA3 {0} \
  266. CONFIG.PCW_USE_TRACE {0} \
  267. CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \
  268. CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \
  269. CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \
  270. CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \
  271. CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \
  272. CONFIG.PCW_USE_CROSS_TRIGGER {0} \
  273. CONFIG.PCW_FTM_CTI_IN0 {<Select>} \
  274. CONFIG.PCW_FTM_CTI_IN1 {<Select>} \
  275. CONFIG.PCW_FTM_CTI_IN2 {<Select>} \
  276. CONFIG.PCW_FTM_CTI_IN3 {<Select>} \
  277. CONFIG.PCW_FTM_CTI_OUT0 {<Select>} \
  278. CONFIG.PCW_FTM_CTI_OUT1 {<Select>} \
  279. CONFIG.PCW_FTM_CTI_OUT2 {<Select>} \
  280. CONFIG.PCW_FTM_CTI_OUT3 {<Select>} \
  281. CONFIG.PCW_USE_DEBUG {0} \
  282. CONFIG.PCW_USE_CR_FABRIC {1} \
  283. CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \
  284. CONFIG.PCW_USE_DDR_BYPASS {0} \
  285. CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
  286. CONFIG.PCW_USE_PROC_EVENT_BUS {0} \
  287. CONFIG.PCW_USE_EXPANDED_IOP {0} \
  288. CONFIG.PCW_USE_HIGH_OCM {0} \
  289. CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \
  290. CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \
  291. CONFIG.PCW_USE_CORESIGHT {0} \
  292. CONFIG.PCW_EN_EMIO_SRAM_INT {0} \
  293. CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
  294. CONFIG.PCW_UART0_BAUD_RATE {115200} \
  295. CONFIG.PCW_UART1_BAUD_RATE {115200} \
  296. CONFIG.PCW_EN_4K_TIMER {0} \
  297. CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \
  298. CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \
  299. CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \
  300. CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \
  301. CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \
  302. CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \
  303. CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \
  304. CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \
  305. CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \
  306. CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \
  307. CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \
  308. CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \
  309. CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \
  310. CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \
  311. CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \
  312. CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \
  313. CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \
  314. CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \
  315. CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \
  316. CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \
  317. CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \
  318. CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \
  319. CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \
  320. CONFIG.PCW_EN_DDR {1} \
  321. CONFIG.PCW_EN_SMC {0} \
  322. CONFIG.PCW_EN_QSPI {1} \
  323. CONFIG.PCW_EN_CAN0 {0} \
  324. CONFIG.PCW_EN_CAN1 {0} \
  325. CONFIG.PCW_EN_ENET0 {1} \
  326. CONFIG.PCW_EN_ENET1 {0} \
  327. CONFIG.PCW_EN_GPIO {0} \
  328. CONFIG.PCW_EN_I2C0 {1} \
  329. CONFIG.PCW_EN_I2C1 {0} \
  330. CONFIG.PCW_EN_PJTAG {0} \
  331. CONFIG.PCW_EN_SDIO0 {1} \
  332. CONFIG.PCW_EN_SDIO1 {0} \
  333. CONFIG.PCW_EN_SPI0 {0} \
  334. CONFIG.PCW_EN_SPI1 {0} \
  335. CONFIG.PCW_EN_UART0 {0} \
  336. CONFIG.PCW_EN_UART1 {1} \
  337. CONFIG.PCW_EN_MODEM_UART0 {0} \
  338. CONFIG.PCW_EN_MODEM_UART1 {0} \
  339. CONFIG.PCW_EN_TTC0 {0} \
  340. CONFIG.PCW_EN_TTC1 {0} \
  341. CONFIG.PCW_EN_WDT {0} \
  342. CONFIG.PCW_EN_TRACE {0} \
  343. CONFIG.PCW_EN_USB0 {1} \
  344. CONFIG.PCW_EN_USB1 {0} \
  345. CONFIG.PCW_DQ_WIDTH {32} \
  346. CONFIG.PCW_DQS_WIDTH {4} \
  347. CONFIG.PCW_DM_WIDTH {4} \
  348. CONFIG.PCW_MIO_PRIMITIVE {54} \
  349. CONFIG.PCW_EN_CLK0_PORT {1} \
  350. CONFIG.PCW_EN_CLK1_PORT {1} \
  351. CONFIG.PCW_EN_CLK2_PORT {1} \
  352. CONFIG.PCW_EN_CLK3_PORT {0} \
  353. CONFIG.PCW_EN_RST0_PORT {1} \
  354. CONFIG.PCW_EN_RST1_PORT {1} \
  355. CONFIG.PCW_EN_RST2_PORT {0} \
  356. CONFIG.PCW_EN_RST3_PORT {0} \
  357. CONFIG.PCW_EN_CLKTRIG0_PORT {0} \
  358. CONFIG.PCW_EN_CLKTRIG1_PORT {0} \
  359. CONFIG.PCW_EN_CLKTRIG2_PORT {0} \
  360. CONFIG.PCW_EN_CLKTRIG3_PORT {0} \
  361. CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \
  362. CONFIG.PCW_P2F_DMAC0_INTR {0} \
  363. CONFIG.PCW_P2F_DMAC1_INTR {0} \
  364. CONFIG.PCW_P2F_DMAC2_INTR {0} \
  365. CONFIG.PCW_P2F_DMAC3_INTR {0} \
  366. CONFIG.PCW_P2F_DMAC4_INTR {0} \
  367. CONFIG.PCW_P2F_DMAC5_INTR {0} \
  368. CONFIG.PCW_P2F_DMAC6_INTR {0} \
  369. CONFIG.PCW_P2F_DMAC7_INTR {0} \
  370. CONFIG.PCW_P2F_SMC_INTR {0} \
  371. CONFIG.PCW_P2F_QSPI_INTR {0} \
  372. CONFIG.PCW_P2F_CTI_INTR {0} \
  373. CONFIG.PCW_P2F_GPIO_INTR {0} \
  374. CONFIG.PCW_P2F_USB0_INTR {0} \
  375. CONFIG.PCW_P2F_ENET0_INTR {0} \
  376. CONFIG.PCW_P2F_SDIO0_INTR {0} \
  377. CONFIG.PCW_P2F_I2C0_INTR {0} \
  378. CONFIG.PCW_P2F_SPI0_INTR {0} \
  379. CONFIG.PCW_P2F_UART0_INTR {0} \
  380. CONFIG.PCW_P2F_CAN0_INTR {0} \
  381. CONFIG.PCW_P2F_USB1_INTR {0} \
  382. CONFIG.PCW_P2F_ENET1_INTR {0} \
  383. CONFIG.PCW_P2F_SDIO1_INTR {0} \
  384. CONFIG.PCW_P2F_I2C1_INTR {0} \
  385. CONFIG.PCW_P2F_SPI1_INTR {0} \
  386. CONFIG.PCW_P2F_UART1_INTR {0} \
  387. CONFIG.PCW_P2F_CAN1_INTR {0} \
  388. CONFIG.PCW_IRQ_F2P_INTR {0} \
  389. CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
  390. CONFIG.PCW_CORE0_FIQ_INTR {0} \
  391. CONFIG.PCW_CORE0_IRQ_INTR {0} \
  392. CONFIG.PCW_CORE1_FIQ_INTR {0} \
  393. CONFIG.PCW_CORE1_IRQ_INTR {0} \
  394. CONFIG.PCW_VALUE_SILVERSION {3} \
  395. CONFIG.PCW_IMPORT_BOARD_PRESET {./lib/xml/ZYBO_zynq_def.xml} \
  396. CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \
  397. CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
  398. CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
  399. CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
  400. CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
  401. CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \
  402. CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
  403. CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
  404. CONFIG.PCW_UIPARAM_DDR_BL {8} \
  405. CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
  406. CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K128M16 JT-125} \
  407. CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
  408. CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \
  409. CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
  410. CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
  411. CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
  412. CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
  413. CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
  414. CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
  415. CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0 {<Select>} \
  416. CONFIG.PCW_DDR_PRIORITY_WRITEPORT_1 {<Select>} \
  417. CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2 {<Select>} \
  418. CONFIG.PCW_DDR_PRIORITY_WRITEPORT_3 {<Select>} \
  419. CONFIG.PCW_DDR_PRIORITY_READPORT_0 {<Select>} \
  420. CONFIG.PCW_DDR_PRIORITY_READPORT_1 {<Select>} \
  421. CONFIG.PCW_DDR_PRIORITY_READPORT_2 {<Select>} \
  422. CONFIG.PCW_DDR_PRIORITY_READPORT_3 {<Select>} \
  423. CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
  424. CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
  425. CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
  426. CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
  427. CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \
  428. CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
  429. CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
  430. CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
  431. CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
  432. CONFIG.PCW_NAND_NAND_IO {<Select>} \
  433. CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
  434. CONFIG.PCW_NAND_GRP_D8_IO {<Select>} \
  435. CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
  436. CONFIG.PCW_NOR_NOR_IO {<Select>} \
  437. CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
  438. CONFIG.PCW_NOR_GRP_A25_IO {<Select>} \
  439. CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
  440. CONFIG.PCW_NOR_GRP_CS0_IO {<Select>} \
  441. CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
  442. CONFIG.PCW_NOR_GRP_SRAM_CS0_IO {<Select>} \
  443. CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
  444. CONFIG.PCW_NOR_GRP_CS1_IO {<Select>} \
  445. CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
  446. CONFIG.PCW_NOR_GRP_SRAM_CS1_IO {<Select>} \
  447. CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
  448. CONFIG.PCW_NOR_GRP_SRAM_INT_IO {<Select>} \
  449. CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
  450. CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
  451. CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
  452. CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
  453. CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
  454. CONFIG.PCW_QSPI_GRP_SS1_IO {<Select>} \
  455. CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
  456. CONFIG.PCW_QSPI_GRP_IO1_IO {<Select>} \
  457. CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
  458. CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
  459. CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
  460. CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
  461. CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
  462. CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
  463. CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
  464. CONFIG.PCW_ENET_RESET_ENABLE {0} \
  465. CONFIG.PCW_ENET_RESET_SELECT {<Select>} \
  466. CONFIG.PCW_ENET0_RESET_ENABLE {0} \
  467. CONFIG.PCW_ENET0_RESET_IO {<Select>} \
  468. CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
  469. CONFIG.PCW_ENET1_ENET1_IO {<Select>} \
  470. CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
  471. CONFIG.PCW_ENET1_GRP_MDIO_IO {<Select>} \
  472. CONFIG.PCW_ENET1_RESET_ENABLE {0} \
  473. CONFIG.PCW_ENET1_RESET_IO {<Select>} \
  474. CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
  475. CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
  476. CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
  477. CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
  478. CONFIG.PCW_SD0_GRP_WP_ENABLE {1} \
  479. CONFIG.PCW_SD0_GRP_WP_IO {EMIO} \
  480. CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
  481. CONFIG.PCW_SD0_GRP_POW_IO {<Select>} \
  482. CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \
  483. CONFIG.PCW_SD1_SD1_IO {<Select>} \
  484. CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
  485. CONFIG.PCW_SD1_GRP_CD_IO {<Select>} \
  486. CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
  487. CONFIG.PCW_SD1_GRP_WP_IO {<Select>} \
  488. CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
  489. CONFIG.PCW_SD1_GRP_POW_IO {<Select>} \
  490. CONFIG.PCW_UART0_PERIPHERAL_ENABLE {0} \
  491. CONFIG.PCW_UART0_UART0_IO {<Select>} \
  492. CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
  493. CONFIG.PCW_UART0_GRP_FULL_IO {<Select>} \
  494. CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
  495. CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
  496. CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
  497. CONFIG.PCW_UART1_GRP_FULL_IO {<Select>} \
  498. CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \
  499. CONFIG.PCW_SPI0_SPI0_IO {<Select>} \
  500. CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \
  501. CONFIG.PCW_SPI0_GRP_SS0_IO {<Select>} \
  502. CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
  503. CONFIG.PCW_SPI0_GRP_SS1_IO {<Select>} \
  504. CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
  505. CONFIG.PCW_SPI0_GRP_SS2_IO {<Select>} \
  506. CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \
  507. CONFIG.PCW_SPI1_SPI1_IO {<Select>} \
  508. CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \
  509. CONFIG.PCW_SPI1_GRP_SS0_IO {<Select>} \
  510. CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \
  511. CONFIG.PCW_SPI1_GRP_SS1_IO {<Select>} \
  512. CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \
  513. CONFIG.PCW_SPI1_GRP_SS2_IO {<Select>} \
  514. CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \
  515. CONFIG.PCW_CAN0_CAN0_IO {<Select>} \
  516. CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \
  517. CONFIG.PCW_CAN0_GRP_CLK_IO {<Select>} \
  518. CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \
  519. CONFIG.PCW_CAN1_CAN1_IO {<Select>} \
  520. CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \
  521. CONFIG.PCW_CAN1_GRP_CLK_IO {<Select>} \
  522. CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \
  523. CONFIG.PCW_TRACE_TRACE_IO {<Select>} \
  524. CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \
  525. CONFIG.PCW_TRACE_GRP_2BIT_IO {<Select>} \
  526. CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \
  527. CONFIG.PCW_TRACE_GRP_4BIT_IO {<Select>} \
  528. CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0} \
  529. CONFIG.PCW_TRACE_GRP_8BIT_IO {<Select>} \
  530. CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \
  531. CONFIG.PCW_TRACE_GRP_16BIT_IO {<Select>} \
  532. CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0} \
  533. CONFIG.PCW_TRACE_GRP_32BIT_IO {<Select>} \
  534. CONFIG.PCW_TRACE_INTERNAL_WIDTH {32} \
  535. CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
  536. CONFIG.PCW_WDT_WDT_IO {<Select>} \
  537. CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} \
  538. CONFIG.PCW_TTC0_TTC0_IO {<Select>} \
  539. CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
  540. CONFIG.PCW_TTC1_TTC1_IO {<Select>} \
  541. CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
  542. CONFIG.PCW_PJTAG_PJTAG_IO {<Select>} \
  543. CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
  544. CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
  545. CONFIG.PCW_USB_RESET_ENABLE {0} \
  546. CONFIG.PCW_USB_RESET_SELECT {<Select>} \
  547. CONFIG.PCW_USB0_RESET_ENABLE {0} \
  548. CONFIG.PCW_USB0_RESET_IO {<Select>} \
  549. CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
  550. CONFIG.PCW_USB1_USB1_IO {<Select>} \
  551. CONFIG.PCW_USB1_RESET_ENABLE {0} \
  552. CONFIG.PCW_USB1_RESET_IO {<Select>} \
  553. CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
  554. CONFIG.PCW_I2C0_I2C0_IO {EMIO} \
  555. CONFIG.PCW_I2C0_GRP_INT_ENABLE {1} \
  556. CONFIG.PCW_I2C0_GRP_INT_IO {EMIO} \
  557. CONFIG.PCW_I2C0_RESET_ENABLE {0} \
  558. CONFIG.PCW_I2C0_RESET_IO {<Select>} \
  559. CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
  560. CONFIG.PCW_I2C1_I2C1_IO {<Select>} \
  561. CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \
  562. CONFIG.PCW_I2C1_GRP_INT_IO {<Select>} \
  563. CONFIG.PCW_I2C_RESET_ENABLE {0} \
  564. CONFIG.PCW_I2C_RESET_SELECT {<Select>} \
  565. CONFIG.PCW_I2C1_RESET_ENABLE {0} \
  566. CONFIG.PCW_I2C1_RESET_IO {<Select>} \
  567. CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {1} \
  568. CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} \
  569. CONFIG.PCW_GPIO_MIO_GPIO_IO {<Select>} \
  570. CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
  571. CONFIG.PCW_GPIO_EMIO_GPIO_IO {<Select>} \
  572. CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
  573. CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
  574. CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
  575. CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
  576. CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
  577. CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
  578. CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
  579. CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
  580. CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
  581. CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \
  582. CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
  583. CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
  584. CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {DDR PLL} \
  585. CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {ARM PLL} \
  586. CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
  587. CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
  588. CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
  589. CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
  590. CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
  591. CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
  592. CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
  593. CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
  594. CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
  595. CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
  596. CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
  597. CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
  598. CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \
  599. CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
  600. CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
  601. CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
  602. CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
  603. CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
  604. CONFIG.PCW_MIO_0_PULLUP {<Select>} \
  605. CONFIG.PCW_MIO_0_IOTYPE {<Select>} \
  606. CONFIG.PCW_MIO_0_DIRECTION {<Select>} \
  607. CONFIG.PCW_MIO_0_SLEW {<Select>} \
  608. CONFIG.PCW_MIO_1_PULLUP {disabled} \
  609. CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
  610. CONFIG.PCW_MIO_1_DIRECTION {out} \
  611. CONFIG.PCW_MIO_1_SLEW {fast} \
  612. CONFIG.PCW_MIO_2_PULLUP {disabled} \
  613. CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
  614. CONFIG.PCW_MIO_2_DIRECTION {inout} \
  615. CONFIG.PCW_MIO_2_SLEW {fast} \
  616. CONFIG.PCW_MIO_3_PULLUP {disabled} \
  617. CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
  618. CONFIG.PCW_MIO_3_DIRECTION {inout} \
  619. CONFIG.PCW_MIO_3_SLEW {fast} \
  620. CONFIG.PCW_MIO_4_PULLUP {disabled} \
  621. CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
  622. CONFIG.PCW_MIO_4_DIRECTION {inout} \
  623. CONFIG.PCW_MIO_4_SLEW {fast} \
  624. CONFIG.PCW_MIO_5_PULLUP {disabled} \
  625. CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
  626. CONFIG.PCW_MIO_5_DIRECTION {inout} \
  627. CONFIG.PCW_MIO_5_SLEW {fast} \
  628. CONFIG.PCW_MIO_6_PULLUP {disabled} \
  629. CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
  630. CONFIG.PCW_MIO_6_DIRECTION {out} \
  631. CONFIG.PCW_MIO_6_SLEW {fast} \
  632. CONFIG.PCW_MIO_7_PULLUP {<Select>} \
  633. CONFIG.PCW_MIO_7_IOTYPE {<Select>} \
  634. CONFIG.PCW_MIO_7_DIRECTION {<Select>} \
  635. CONFIG.PCW_MIO_7_SLEW {<Select>} \
  636. CONFIG.PCW_MIO_8_PULLUP {disabled} \
  637. CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
  638. CONFIG.PCW_MIO_8_DIRECTION {out} \
  639. CONFIG.PCW_MIO_8_SLEW {fast} \
  640. CONFIG.PCW_MIO_9_PULLUP {<Select>} \
  641. CONFIG.PCW_MIO_9_IOTYPE {<Select>} \
  642. CONFIG.PCW_MIO_9_DIRECTION {<Select>} \
  643. CONFIG.PCW_MIO_9_SLEW {<Select>} \
  644. CONFIG.PCW_MIO_10_PULLUP {<Select>} \
  645. CONFIG.PCW_MIO_10_IOTYPE {<Select>} \
  646. CONFIG.PCW_MIO_10_DIRECTION {<Select>} \
  647. CONFIG.PCW_MIO_10_SLEW {<Select>} \
  648. CONFIG.PCW_MIO_11_PULLUP {<Select>} \
  649. CONFIG.PCW_MIO_11_IOTYPE {<Select>} \
  650. CONFIG.PCW_MIO_11_DIRECTION {<Select>} \
  651. CONFIG.PCW_MIO_11_SLEW {<Select>} \
  652. CONFIG.PCW_MIO_12_PULLUP {<Select>} \
  653. CONFIG.PCW_MIO_12_IOTYPE {<Select>} \
  654. CONFIG.PCW_MIO_12_DIRECTION {<Select>} \
  655. CONFIG.PCW_MIO_12_SLEW {<Select>} \
  656. CONFIG.PCW_MIO_13_PULLUP {<Select>} \
  657. CONFIG.PCW_MIO_13_IOTYPE {<Select>} \
  658. CONFIG.PCW_MIO_13_DIRECTION {<Select>} \
  659. CONFIG.PCW_MIO_13_SLEW {<Select>} \
  660. CONFIG.PCW_MIO_14_PULLUP {<Select>} \
  661. CONFIG.PCW_MIO_14_IOTYPE {<Select>} \
  662. CONFIG.PCW_MIO_14_DIRECTION {<Select>} \
  663. CONFIG.PCW_MIO_14_SLEW {<Select>} \
  664. CONFIG.PCW_MIO_15_PULLUP {<Select>} \
  665. CONFIG.PCW_MIO_15_IOTYPE {<Select>} \
  666. CONFIG.PCW_MIO_15_DIRECTION {<Select>} \
  667. CONFIG.PCW_MIO_15_SLEW {<Select>} \
  668. CONFIG.PCW_MIO_16_PULLUP {disabled} \
  669. CONFIG.PCW_MIO_16_IOTYPE {HSTL 1.8V} \
  670. CONFIG.PCW_MIO_16_DIRECTION {out} \
  671. CONFIG.PCW_MIO_16_SLEW {fast} \
  672. CONFIG.PCW_MIO_17_PULLUP {disabled} \
  673. CONFIG.PCW_MIO_17_IOTYPE {HSTL 1.8V} \
  674. CONFIG.PCW_MIO_17_DIRECTION {out} \
  675. CONFIG.PCW_MIO_17_SLEW {fast} \
  676. CONFIG.PCW_MIO_18_PULLUP {disabled} \
  677. CONFIG.PCW_MIO_18_IOTYPE {HSTL 1.8V} \
  678. CONFIG.PCW_MIO_18_DIRECTION {out} \
  679. CONFIG.PCW_MIO_18_SLEW {fast} \
  680. CONFIG.PCW_MIO_19_PULLUP {disabled} \
  681. CONFIG.PCW_MIO_19_IOTYPE {HSTL 1.8V} \
  682. CONFIG.PCW_MIO_19_DIRECTION {out} \
  683. CONFIG.PCW_MIO_19_SLEW {fast} \
  684. CONFIG.PCW_MIO_20_PULLUP {disabled} \
  685. CONFIG.PCW_MIO_20_IOTYPE {HSTL 1.8V} \
  686. CONFIG.PCW_MIO_20_DIRECTION {out} \
  687. CONFIG.PCW_MIO_20_SLEW {fast} \
  688. CONFIG.PCW_MIO_21_PULLUP {disabled} \
  689. CONFIG.PCW_MIO_21_IOTYPE {HSTL 1.8V} \
  690. CONFIG.PCW_MIO_21_DIRECTION {out} \
  691. CONFIG.PCW_MIO_21_SLEW {fast} \
  692. CONFIG.PCW_MIO_22_PULLUP {disabled} \
  693. CONFIG.PCW_MIO_22_IOTYPE {HSTL 1.8V} \
  694. CONFIG.PCW_MIO_22_DIRECTION {in} \
  695. CONFIG.PCW_MIO_22_SLEW {fast} \
  696. CONFIG.PCW_MIO_23_PULLUP {disabled} \
  697. CONFIG.PCW_MIO_23_IOTYPE {HSTL 1.8V} \
  698. CONFIG.PCW_MIO_23_DIRECTION {in} \
  699. CONFIG.PCW_MIO_23_SLEW {fast} \
  700. CONFIG.PCW_MIO_24_PULLUP {disabled} \
  701. CONFIG.PCW_MIO_24_IOTYPE {HSTL 1.8V} \
  702. CONFIG.PCW_MIO_24_DIRECTION {in} \
  703. CONFIG.PCW_MIO_24_SLEW {fast} \
  704. CONFIG.PCW_MIO_25_PULLUP {disabled} \
  705. CONFIG.PCW_MIO_25_IOTYPE {HSTL 1.8V} \
  706. CONFIG.PCW_MIO_25_DIRECTION {in} \
  707. CONFIG.PCW_MIO_25_SLEW {fast} \
  708. CONFIG.PCW_MIO_26_PULLUP {disabled} \
  709. CONFIG.PCW_MIO_26_IOTYPE {HSTL 1.8V} \
  710. CONFIG.PCW_MIO_26_DIRECTION {in} \
  711. CONFIG.PCW_MIO_26_SLEW {fast} \
  712. CONFIG.PCW_MIO_27_PULLUP {disabled} \
  713. CONFIG.PCW_MIO_27_IOTYPE {HSTL 1.8V} \
  714. CONFIG.PCW_MIO_27_DIRECTION {in} \
  715. CONFIG.PCW_MIO_27_SLEW {fast} \
  716. CONFIG.PCW_MIO_28_PULLUP {disabled} \
  717. CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
  718. CONFIG.PCW_MIO_28_DIRECTION {inout} \
  719. CONFIG.PCW_MIO_28_SLEW {fast} \
  720. CONFIG.PCW_MIO_29_PULLUP {disabled} \
  721. CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
  722. CONFIG.PCW_MIO_29_DIRECTION {in} \
  723. CONFIG.PCW_MIO_29_SLEW {fast} \
  724. CONFIG.PCW_MIO_30_PULLUP {disabled} \
  725. CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
  726. CONFIG.PCW_MIO_30_DIRECTION {out} \
  727. CONFIG.PCW_MIO_30_SLEW {fast} \
  728. CONFIG.PCW_MIO_31_PULLUP {disabled} \
  729. CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
  730. CONFIG.PCW_MIO_31_DIRECTION {in} \
  731. CONFIG.PCW_MIO_31_SLEW {fast} \
  732. CONFIG.PCW_MIO_32_PULLUP {disabled} \
  733. CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
  734. CONFIG.PCW_MIO_32_DIRECTION {inout} \
  735. CONFIG.PCW_MIO_32_SLEW {fast} \
  736. CONFIG.PCW_MIO_33_PULLUP {disabled} \
  737. CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
  738. CONFIG.PCW_MIO_33_DIRECTION {inout} \
  739. CONFIG.PCW_MIO_33_SLEW {fast} \
  740. CONFIG.PCW_MIO_34_PULLUP {disabled} \
  741. CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
  742. CONFIG.PCW_MIO_34_DIRECTION {inout} \
  743. CONFIG.PCW_MIO_34_SLEW {fast} \
  744. CONFIG.PCW_MIO_35_PULLUP {disabled} \
  745. CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
  746. CONFIG.PCW_MIO_35_DIRECTION {inout} \
  747. CONFIG.PCW_MIO_35_SLEW {fast} \
  748. CONFIG.PCW_MIO_36_PULLUP {disabled} \
  749. CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
  750. CONFIG.PCW_MIO_36_DIRECTION {in} \
  751. CONFIG.PCW_MIO_36_SLEW {fast} \
  752. CONFIG.PCW_MIO_37_PULLUP {disabled} \
  753. CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
  754. CONFIG.PCW_MIO_37_DIRECTION {inout} \
  755. CONFIG.PCW_MIO_37_SLEW {fast} \
  756. CONFIG.PCW_MIO_38_PULLUP {disabled} \
  757. CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
  758. CONFIG.PCW_MIO_38_DIRECTION {inout} \
  759. CONFIG.PCW_MIO_38_SLEW {fast} \
  760. CONFIG.PCW_MIO_39_PULLUP {disabled} \
  761. CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
  762. CONFIG.PCW_MIO_39_DIRECTION {inout} \
  763. CONFIG.PCW_MIO_39_SLEW {fast} \
  764. CONFIG.PCW_MIO_40_PULLUP {disabled} \
  765. CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
  766. CONFIG.PCW_MIO_40_DIRECTION {inout} \
  767. CONFIG.PCW_MIO_40_SLEW {fast} \
  768. CONFIG.PCW_MIO_41_PULLUP {disabled} \
  769. CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
  770. CONFIG.PCW_MIO_41_DIRECTION {inout} \
  771. CONFIG.PCW_MIO_41_SLEW {fast} \
  772. CONFIG.PCW_MIO_42_PULLUP {disabled} \
  773. CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
  774. CONFIG.PCW_MIO_42_DIRECTION {inout} \
  775. CONFIG.PCW_MIO_42_SLEW {fast} \
  776. CONFIG.PCW_MIO_43_PULLUP {disabled} \
  777. CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
  778. CONFIG.PCW_MIO_43_DIRECTION {inout} \
  779. CONFIG.PCW_MIO_43_SLEW {fast} \
  780. CONFIG.PCW_MIO_44_PULLUP {disabled} \
  781. CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
  782. CONFIG.PCW_MIO_44_DIRECTION {inout} \
  783. CONFIG.PCW_MIO_44_SLEW {fast} \
  784. CONFIG.PCW_MIO_45_PULLUP {disabled} \
  785. CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
  786. CONFIG.PCW_MIO_45_DIRECTION {inout} \
  787. CONFIG.PCW_MIO_45_SLEW {fast} \
  788. CONFIG.PCW_MIO_46_PULLUP {<Select>} \
  789. CONFIG.PCW_MIO_46_IOTYPE {<Select>} \
  790. CONFIG.PCW_MIO_46_DIRECTION {<Select>} \
  791. CONFIG.PCW_MIO_46_SLEW {<Select>} \
  792. CONFIG.PCW_MIO_47_PULLUP {enabled} \
  793. CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
  794. CONFIG.PCW_MIO_47_DIRECTION {in} \
  795. CONFIG.PCW_MIO_47_SLEW {slow} \
  796. CONFIG.PCW_MIO_48_PULLUP {disabled} \
  797. CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
  798. CONFIG.PCW_MIO_48_DIRECTION {out} \
  799. CONFIG.PCW_MIO_48_SLEW {slow} \
  800. CONFIG.PCW_MIO_49_PULLUP {disabled} \
  801. CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
  802. CONFIG.PCW_MIO_49_DIRECTION {in} \
  803. CONFIG.PCW_MIO_49_SLEW {slow} \
  804. CONFIG.PCW_MIO_50_PULLUP {<Select>} \
  805. CONFIG.PCW_MIO_50_IOTYPE {<Select>} \
  806. CONFIG.PCW_MIO_50_DIRECTION {<Select>} \
  807. CONFIG.PCW_MIO_50_SLEW {<Select>} \
  808. CONFIG.PCW_MIO_51_PULLUP {<Select>} \
  809. CONFIG.PCW_MIO_51_IOTYPE {<Select>} \
  810. CONFIG.PCW_MIO_51_DIRECTION {<Select>} \
  811. CONFIG.PCW_MIO_51_SLEW {<Select>} \
  812. CONFIG.PCW_MIO_52_PULLUP {disabled} \
  813. CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
  814. CONFIG.PCW_MIO_52_DIRECTION {out} \
  815. CONFIG.PCW_MIO_52_SLEW {slow} \
  816. CONFIG.PCW_MIO_53_PULLUP {disabled} \
  817. CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
  818. CONFIG.PCW_MIO_53_DIRECTION {inout} \
  819. CONFIG.PCW_MIO_53_SLEW {slow} \
  820. CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \
  821. CONFIG.PCW_MIO_TREE_PERIPHERALS {unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#Quad SPI Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#unassigned#SD 0#UART 1#UART 1#unassigned#unassigned#Enet 0#Enet 0} \
  822. CONFIG.PCW_MIO_TREE_SIGNALS {unassigned#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#unassigned#qspi_fbclk#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#unassigned#cd#tx#rx#unassigned#unassigned#mdc#mdio} \
  823. CONFIG.PCW_PS7_SI_REV {PRODUCTION} \
  824. CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
  825. CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \
  826. CONFIG.PCW_FPGA_FCLK2_ENABLE {1} \
  827. CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
  828. CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \
  829. CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \
  830. CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \
  831. CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \
  832. CONFIG.PCW_NOR_SRAM_CS0_T_WC {2} \
  833. CONFIG.PCW_NOR_SRAM_CS0_T_RC {2} \
  834. CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {2} \
  835. CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \
  836. CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \
  837. CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \
  838. CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \
  839. CONFIG.PCW_NOR_SRAM_CS1_T_WC {2} \
  840. CONFIG.PCW_NOR_SRAM_CS1_T_RC {2} \
  841. CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {2} \
  842. CONFIG.PCW_NOR_CS0_T_TR {1} \
  843. CONFIG.PCW_NOR_CS0_T_PC {1} \
  844. CONFIG.PCW_NOR_CS0_T_WP {1} \
  845. CONFIG.PCW_NOR_CS0_T_CEOE {1} \
  846. CONFIG.PCW_NOR_CS0_T_WC {2} \
  847. CONFIG.PCW_NOR_CS0_T_RC {2} \
  848. CONFIG.PCW_NOR_CS0_WE_TIME {2} \
  849. CONFIG.PCW_NOR_CS1_T_TR {1} \
  850. CONFIG.PCW_NOR_CS1_T_PC {1} \
  851. CONFIG.PCW_NOR_CS1_T_WP {1} \
  852. CONFIG.PCW_NOR_CS1_T_CEOE {1} \
  853. CONFIG.PCW_NOR_CS1_T_WC {2} \
  854. CONFIG.PCW_NOR_CS1_T_RC {2} \
  855. CONFIG.PCW_NOR_CS1_WE_TIME {2} \
  856. CONFIG.PCW_NAND_CYCLES_T_RR {0} \
  857. CONFIG.PCW_NAND_CYCLES_T_AR {0} \
  858. CONFIG.PCW_NAND_CYCLES_T_CLR {0} \
  859. CONFIG.PCW_NAND_CYCLES_T_WP {1} \
  860. CONFIG.PCW_NAND_CYCLES_T_REA {1} \
  861. CONFIG.PCW_NAND_CYCLES_T_WC {2} \
  862. CONFIG.PCW_NAND_CYCLES_T_RC {2} \
  863. CONFIG.PCW_SMC_CYCLE_T0 {NA} \
  864. CONFIG.PCW_SMC_CYCLE_T1 {NA} \
  865. CONFIG.PCW_SMC_CYCLE_T2 {NA} \
  866. CONFIG.PCW_SMC_CYCLE_T3 {NA} \
  867. CONFIG.PCW_SMC_CYCLE_T4 {NA} \
  868. CONFIG.PCW_SMC_CYCLE_T5 {NA} \
  869. CONFIG.PCW_SMC_CYCLE_T6 {NA} \
  870. CONFIG.PCW_PACKAGE_NAME {clg400} \
  871. ]
  872. }
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