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-- Company:
-- Engineer:
--
-- Create Date:    20:58:27 10/26/2016
-- Design Name:
-- Module Name:    carry_adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity carry_adder is
  port(
            A : in std_logic_vector(3 downto 0);
            B : in std_logic_vector (3  downto 0);
            carryIn : in std_logic ;
            carryOut : out std_logic;
            result : out std_logic_vector( 3 downto 0)
            );
-- defining signals used

signal carryGenerate : std_logic_vector(3 downto 0);
signal carryPropagate : std_logic_vector(3 downto 0);
signal carryInternal : std_logic_vector(3 downto 0);



end carry_adder;

architecture Behavioral of carry_adder is

begin

process (A,B,carryPropagate,carryInternal,carryGenerate)
begin

 carryPropagate <= A xor B;
 carryGenerate <= A and B;
 carryInternal(1) <= carryGenerate(0) or (carryPropagate(0) and carryIn);

 inst :for i in 1 to 2 loop
 carryInternal(i+1) <= carryGenerate(1) or (carryPropagate(i) and carryInternal(i));
 end loop;
 carryOut <= carryGenerate(3) or (carryPropagate(3) and carryInternal(3));
        result(0) <= carryPropagate(0) xor carryIn;
        result(3 downto 1) <= carryPropagate(3 downto 1) xor carryInternal(3 downto 1);


end process;

end Behavioral;