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  1. /*
  2.  * This program is free software; you can redistribute it and/or modify
  3.  * it under the terms of the GNU General Public License as published by
  4.  * the Free Software Foundation; either version 2 of the License, or
  5.  * (at your option) any later version.
  6.  */
  7.  
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/sched.h>
  11. #include <linux/init.h>
  12. #include <linux/cpu.h>
  13. #include <linux/cpufreq.h>
  14. #include <linux/delay.h>
  15. #include <linux/slab.h>
  16. #include <linux/proc_fs.h>
  17. #include <linux/miscdevice.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/earlysuspend.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/kthread.h>
  22. #include <linux/hrtimer.h>
  23. #include <linux/ktime.h>
  24. #include <linux/xlog.h>
  25. #include <linux/jiffies.h>
  26.  
  27. #include <asm/system.h>
  28. #include <asm/uaccess.h>
  29.  
  30. #include "mach/mt_typedefs.h"
  31. #include "mach/mt_clkmgr.h"
  32. #include "mach/mt_cpufreq.h"
  33. #include "mach/sync_write.h"
  34.  
  35. #include <mach/pmic_mt6320_sw.h>
  36. #include <mach/upmu_common.h>
  37. #include <mach/upmu_hw.h>
  38.  
  39. /**************************************************
  40. * enable for DVFS random test
  41. ***************************************************/
  42. //#define MT_DVFS_RANDOM_TEST
  43.  
  44. /**************************************************
  45. * enable this option to adjust buck voltage
  46. ***************************************************/
  47. #define MT_BUCK_ADJUST
  48.  
  49. /***************************
  50. * debug message
  51. ****************************/
  52. #define dprintk(fmt, args...)                                       \
  53. do {                                                                \
  54.     if (mt_cpufreq_debug) {                                         \
  55.         xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", fmt, ##args);   \
  56.     }                                                               \
  57. } while(0)
  58.  
  59. #define ARRAY_AND_SIZE(x)   (x), ARRAY_SIZE(x)
  60.  
  61. #ifdef CONFIG_HAS_EARLYSUSPEND
  62. static struct early_suspend mt_cpufreq_early_suspend_handler =
  63. {
  64.     .level = EARLY_SUSPEND_LEVEL_DISABLE_FB + 200,
  65.     .suspend = NULL,
  66.     .resume  = NULL,
  67. };
  68. #endif
  69.  
  70. #define DVFS_F0_0   (1703000)   // KHz
  71. #define DVFS_F0_1   (1599000)   // KHz
  72. #define DVFS_F0_2   (1508000)   // KHz
  73. #define DVFS_F0_3   (1404000)   // KHz
  74. #define DVFS_F0_4   (1300000)   // KHz
  75. #define DVFS_F1     (1209000)   // KHz
  76. #define DVFS_F2     ( 988000)   // KHz
  77. #define DVFS_F3     ( 754000)   // KHz
  78. #define DVFS_F4     ( 497250)   // KHz
  79.  
  80. #define DVFS_V0     (1250)  // mV
  81. #define DVFS_V1     (1200)  // mV
  82. #define DVFS_V2     (1150)  // mV
  83. #define DVFS_V3     (1050)  // mV
  84. #define DVFS_V4     ( 950)  // mV
  85.  
  86. /*****************************************
  87. * PMIC settle time, should not be changed
  88. ******************************************/
  89. #define PMIC_SETTLE_TIME (40) // us
  90.  
  91. /*****************************************
  92. * PLL settle time, should not be changed
  93. ******************************************/
  94. #define PLL_SETTLE_TIME (30) // us
  95.  
  96. /*****************************************
  97. * MT6320 DVS DOWN settle time, should not be changed
  98. ******************************************/
  99. #define DVS_DOWN_SETTLE_TIME (120) // us
  100.  
  101. /***********************************************
  102. * RMAP DOWN TIMES to postpone frequency degrade
  103. ************************************************/
  104. #define RAMP_DOWN_TIMES (2)
  105.  
  106. /**********************************
  107. * Available Clock Source for CPU
  108. ***********************************/
  109. #define TOP_CKMUXSEL_CLKSQ   0x0
  110. #define TOP_CKMUXSEL_ARMPLL  0x1
  111. #define TOP_CKMUXSEL_MAINPLL 0x2
  112. #define TOP_CKMUXSEL_MMPLL   0x3
  113.  
  114. #define MIN_FREQ_EARLY_SUSPEND //EricHsieh,2013/5/20,Using DVFS at early suspend mode
  115.  
  116. /**************************************************
  117. * enable DVFS function
  118. ***************************************************/
  119. static int g_dvfs_disable_count = 0;
  120.  
  121. static unsigned int g_cur_freq;
  122. static unsigned int g_cur_cpufreq_volt;
  123. static unsigned int g_limited_max_ncpu;
  124. static unsigned int g_limited_max_freq;
  125. static unsigned int g_limited_min_freq;
  126. static unsigned int g_cpufreq_get_ptp_level = 1;
  127. static unsigned int g_max_freq_by_ptp = DVFS_F0_4; /* default 1.3GHz */
  128.  
  129. static int g_ramp_down_count = 0;
  130.  
  131. static bool mt_cpufreq_debug = false;
  132. static bool mt_cpufreq_ready = false;
  133. static bool mt_cpufreq_pause = false;
  134. static bool mt_cpufreq_ptpod_disable = false;
  135. static bool mt_cpufreq_ptpod_voltage_down = false;
  136. static bool mt_cpufreq_max_freq_overdrive = false;
  137. static bool mt_cpufreq_limit_max_freq_early_suspend = false;
  138.  
  139. //<<EricHsieh,2013/5/20,Using DVFS at early suspend mode
  140. #ifdef MIN_FREQ_EARLY_SUSPEND
  141. static bool mt_cpufreq_limit_min_freq_early_suspend = false;
  142. static unsigned int early_suspnd_freq = DVFS_F3;
  143. static bool eraly_suspend_dvfs = true;
  144. #endif
  145. //>>EricHsieh,2013/5/20,Using DVFS at early suspend mode
  146.  
  147. /* pmic volt by PTP-OD */
  148. static unsigned int mt_cpufreq_pmic_volt[8] = {0};
  149.  
  150. static DEFINE_SPINLOCK(mt_cpufreq_lock);
  151.  
  152. /***************************
  153. * Operate Point Definition
  154. ****************************/
  155. #define OP(khz, volt)       \
  156. {                           \
  157.     .cpufreq_khz = khz,     \
  158.     .cpufreq_volt = volt,   \
  159. }
  160.  
  161. struct mt_cpu_freq_info
  162. {
  163.     unsigned int cpufreq_khz;
  164.     unsigned int cpufreq_volt;
  165. };
  166.  
  167. struct mt_cpu_power_info
  168. {
  169.     unsigned int cpufreq_khz;
  170.     unsigned int cpufreq_ncpu;
  171.     unsigned int cpufreq_power;
  172. };
  173.  
  174. /***************************
  175. * MT6589 E1 DVFS Table
  176. ****************************/
  177. static struct mt_cpu_freq_info mt6589_freqs_e1[] = {
  178.     OP(DVFS_F1, DVFS_V1),
  179.     OP(DVFS_F2, DVFS_V2),
  180.     OP(DVFS_F3, DVFS_V3),
  181.     OP(DVFS_F4, DVFS_V4),
  182. };
  183.  
  184. static struct mt_cpu_freq_info mt6589_freqs_e1_0[] = {
  185.     OP(DVFS_F0_0, DVFS_V0),
  186.     OP(DVFS_F1, DVFS_V1),
  187.     OP(DVFS_F2, DVFS_V2),
  188.     OP(DVFS_F3, DVFS_V3),
  189.     OP(DVFS_F4, DVFS_V4),
  190. };
  191.  
  192. static struct mt_cpu_freq_info mt6589_freqs_e1_1[] = {
  193.     OP(DVFS_F0_1, DVFS_V0),
  194.     OP(DVFS_F1, DVFS_V1),
  195.     OP(DVFS_F2, DVFS_V2),
  196.     OP(DVFS_F3, DVFS_V3),
  197.     OP(DVFS_F4, DVFS_V4),
  198. };
  199.  
  200. static struct mt_cpu_freq_info mt6589_freqs_e1_2[] = {
  201.     OP(DVFS_F0_2, DVFS_V0),
  202.     OP(DVFS_F1, DVFS_V1),
  203.     OP(DVFS_F2, DVFS_V2),
  204.     OP(DVFS_F3, DVFS_V3),
  205.     OP(DVFS_F4, DVFS_V4),
  206. };
  207.  
  208. static struct mt_cpu_freq_info mt6589_freqs_e1_3[] = {
  209.     OP(DVFS_F0_3, DVFS_V0),
  210.     OP(DVFS_F1, DVFS_V1),
  211.     OP(DVFS_F2, DVFS_V2),
  212.     OP(DVFS_F3, DVFS_V3),
  213.     OP(DVFS_F4, DVFS_V4),
  214. };
  215.  
  216. static struct mt_cpu_freq_info mt6589_freqs_e1_4[] = {
  217.     OP(DVFS_F0_4, DVFS_V0),
  218.     OP(DVFS_F1, DVFS_V1),
  219.     OP(DVFS_F2, DVFS_V2),
  220.     OP(DVFS_F3, DVFS_V3),
  221.     OP(DVFS_F4, DVFS_V4),
  222. };
  223.  
  224. static unsigned int mt_cpu_freqs_num;
  225. static struct mt_cpu_freq_info *mt_cpu_freqs = NULL;
  226. static struct cpufreq_frequency_table *mt_cpu_freqs_table;
  227. static struct mt_cpu_power_info *mt_cpu_power = NULL;
  228.  
  229. /******************************
  230. * Internal Function Declaration
  231. *******************************/
  232. static void mt_cpufreq_volt_set(unsigned int target_volt);
  233.  
  234. /******************************
  235. * Extern Function Declaration
  236. *******************************/
  237. extern int spm_dvfs_ctrl_volt(u32 value);
  238. extern int mtk_cpufreq_register(struct mt_cpu_power_info *freqs, int num);
  239. extern void hp_limited_cpu_num(int num);
  240. extern u32 PTP_get_ptp_level(void);
  241.  
  242. /***********************************************
  243. * MT6589 E1 Raw Data: 1.3Ghz @ 1.15V @ TT 125C
  244. ************************************************/
  245. #define P_MCU_L         (357)   // MCU Leakage Power
  246. #define P_MCU_T         (1228)  // MCU Total Power
  247. #define P_CA7_L         (56)    // CA7 Leakage Power
  248. #define P_CA7_T         (256)   // Single CA7 Core Power
  249.  
  250. #define P_MCL99_105C_L  (632)   // MCL99 Leakage Power @ 105C
  251. #define P_MCL99_25C_L   (54)    // MCL99 Leakage Power @ 25C
  252. #define P_MCL50_105C_L  (211)   // MCL50 Leakage Power @ 105C
  253. #define P_MCL50_25C_L   (18)    // MCL50 Leakage Power @ 25C
  254.  
  255. #define T_105           (105)   // Temperature 105C
  256. #define T_60            (60)    // Temperature 60C
  257. #define T_25            (25)    // Temperature 25C
  258.  
  259. #define P_MCU_D ((P_MCU_T - P_MCU_L) - 4 * (P_CA7_T - P_CA7_L)) // MCU dynamic power except of CA7 cores
  260.  
  261. #define P_TOTAL_CORE_L (P_MCL99_25C_L + (((((P_MCL99_105C_L - P_MCL99_25C_L) * 100) / (T_105 - T_25)) * (T_60 - T_25)) / 100)) // Total leakage at T_60
  262. #define P_EACH_CORE_L  ((P_TOTAL_CORE_L * ((P_CA7_L * 1000) / P_MCU_L)) / 1000) // 1 core leakage at T_60
  263.  
  264. #define P_CA7_D_1_CORE ((P_CA7_T - P_CA7_L) * 1) // CA7 dynamic power for 1 cores turned on
  265. #define P_CA7_D_2_CORE ((P_CA7_T - P_CA7_L) * 2) // CA7 dynamic power for 2 cores turned on
  266. #define P_CA7_D_3_CORE ((P_CA7_T - P_CA7_L) * 3) // CA7 dynamic power for 3 cores turned on
  267. #define P_CA7_D_4_CORE ((P_CA7_T - P_CA7_L) * 4) // CA7 dynamic power for 4 cores turned on
  268.  
  269. #define A_1_CORE (P_MCU_D + P_CA7_D_1_CORE) // MCU dynamic power for 1 cores turned on
  270. #define A_2_CORE (P_MCU_D + P_CA7_D_2_CORE) // MCU dynamic power for 2 cores turned on
  271. #define A_3_CORE (P_MCU_D + P_CA7_D_3_CORE) // MCU dynamic power for 3 cores turned on
  272. #define A_4_CORE (P_MCU_D + P_CA7_D_4_CORE) // MCU dynamic power for 4 cores turned on
  273.  
  274. #ifdef CPU_DVS_DOWN_SW_SOL
  275. /* MT6320 DVS down software solution. */
  276. static void pmic_dvs_init_setting(void)
  277. {
  278.     int ret=0;
  279. //<2013/04/04-23553-stevenchen, [Pelican][MTK] Patch of fixing abnormal standby current after wake then sleep again.
  280.     ret=pmic_config_interface(0x216, 0x23, 0x7F, 0);   // set 0x35 to Reg[0x216] bit 6:0
  281. //>2013/04/04-23553-stevenchen
  282.  
  283.     ret=pmic_config_interface(0x22A, 0x0, 0x3, 4);      // set 0x0 to Reg[0x22A] bit 5:4
  284.  
  285. //<2013/04/04-23553-stevenchen, [Pelican][MTK] Patch of fixing abnormal standby current after wake then sleep again.
  286.     ret=pmic_config_interface(0x23C, 0x23, 0x7F, 0);  // set 0x35 to Reg[0x23C] bit 6:0
  287. //>2013/04/04-23553-stevenchen
  288.  
  289.     ret=pmic_config_interface(0x22E, 0x2, 0x3, 6);      // set 0x2 to Reg[0x22E] bit 7:6
  290.     ret=pmic_config_interface(0x250, 0x1, 0x3, 4);      // set 0x1 to Reg[0x250] bit 5:4
  291.     ret=pmic_config_interface(0x252, 0x8, 0x7F, 0);  // set 0x8 to Reg[0x252] bit 6:0 (set VSRAM settling voltage offset=50mV)
  292. }
  293.  
  294. static void pmic_dvs_set_before_volt_change(void)
  295. {
  296.     int ret=0;
  297.     ret=pmic_config_interface(0x22A, 0x0, 0x3, 4);      // set 0x0 to Reg[0x22A] bit 5:4
  298.     ret=pmic_config_interface(0x250, 0x1, 0x3, 4);      // set 0x0 to Reg[0x250] bit 5:4
  299.     ret=pmic_config_interface(0x20A, 0x1, 0x1, 8);  // set 0x1 to Reg[0x20A] bit 8 (enable force PWM before voltage change)
  300. }
  301.  
  302. static void pmic_dvs_set_after_volt_settle(void)
  303. {
  304.     int ret=0;
  305.     ret=pmic_config_interface(0x252, 0x8, 0x7F, 0); // set 0x8 to Reg[0x252] bit 6:0 (set VSRAM settling voltage offset=50mV)
  306.     ret=pmic_config_interface(0x230, 0x0, 0x1, 8); // set 0x0 to Reg[0x230] bit 8 (disable VSRAM force PWM after voltage settle)
  307.     ret=pmic_config_interface(0x20A, 0x0, 0x1, 8); // set 0x0 to Reg[0x20A] bit 8 (disable VPROC force PWM after voltage settle)
  308. }
  309.  
  310. void pmic_dvs_into_highest_level_set_before_volt_change(void)
  311. {
  312.     int ret=0;
  313.     ret=pmic_config_interface(0x20A, 0x1, 0x1, 8);  // set 0x1 to Reg[0x20A] bit 8 (enable VPROC force PWM before voltage change)
  314.     ret=pmic_config_interface(0x230, 0x1, 0x1, 8);  // set 0x1 to Reg[0x230] bit 8 (enable VSRAM force PWM before voltage change)
  315.     ret=pmic_config_interface(0x252, 0x0, 0x7F, 0);  // set 0x4 to Reg[0x252] bit 6:0 (set VSRAM settling voltage offset=0mV)
  316. }
  317.  
  318. void pmic_dvs_into_suspend_set_before_volt_change(void)
  319. {
  320.     int ret=0;
  321.     ret=pmic_config_interface(0x252, 0x8, 0x7F, 0);  // set 0x8 to Reg[0x252] bit 6:0 (set VSRAM settling voltage offset=50mV)
  322.     ret=pmic_config_interface(0x20A, 0x0, 0x1, 8);  // set 0x0 to Reg[0x20A] bit 8 (disable VPROC force PWM before voltage change)
  323.     ret=pmic_config_interface(0x230, 0x0, 0x1, 8);  // set 0x0 to Reg[0x230] bit 8 (disable VSRAM force PWM after voltage settle)
  324. }
  325.  
  326. #endif
  327.  
  328. /************************************************
  329. * Limited max frequency in 1.2GHz when early suspend
  330. *************************************************/
  331. static unsigned int mt_cpufreq_limit_max_freq_by_early_suspend(void)
  332. {
  333.     struct cpufreq_policy *policy;
  334.  
  335.     policy = cpufreq_cpu_get(0);
  336.  
  337.     if (!policy)
  338.         goto no_policy;
  339.  
  340.     cpufreq_driver_target(policy, DVFS_F0_4, CPUFREQ_RELATION_L);
  341.  
  342.     xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "mt_cpufreq limited max freq by early suspend %d\n", DVFS_F0_4);
  343.  
  344.     cpufreq_cpu_put(policy);
  345.  
  346. no_policy:
  347.     return g_cur_freq;
  348. }
  349.  
  350. //<<EricHsieh,2013/5/20,Using DVFS at early suspend mode
  351. #ifdef MIN_FREQ_EARLY_SUSPEND
  352. /************************************************
  353. * Limited min frequency in 500MHz when early suspend
  354. *************************************************/
  355. static unsigned int mt_cpufreq_limit_min_freq_by_early_suspend(void)
  356. {
  357.     struct cpufreq_policy *policy;
  358.  
  359.     policy = cpufreq_cpu_get(0);
  360.  
  361.     if (!policy)
  362.         goto no_policy;
  363.  
  364.     cpufreq_driver_target(policy, early_suspnd_freq, CPUFREQ_RELATION_L);
  365.  
  366.     xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "mt_cpufreq limited max freq by early suspend %d\n", early_suspnd_freq);
  367.  
  368.     cpufreq_cpu_put(policy);
  369.  
  370. no_policy:
  371.     return g_cur_freq;
  372. }
  373. #endif
  374. //>>EricHsieh,2013/5/20,Using DVFS at early suspend mode
  375.  
  376. /* Check the mapping for DVFS voltage and pmic wrap voltage */
  377. /* Need sync with mt_cpufreq_volt_set(), mt_cpufreq_pdrv_probe() */
  378. static unsigned int mt_cpufreq_volt_to_pmic_wrap(unsigned int target_volt)
  379. {
  380.     unsigned int idx = 0;
  381.    
  382.     if(g_cpufreq_get_ptp_level == 0)
  383.     {
  384.         switch (target_volt)
  385.         {
  386.             case DVFS_V1:
  387.                 idx = 0;  // spm_dvfs_ctrl_volt(0);
  388.                 break;
  389.             case DVFS_V2:
  390.                 idx = 1;  // spm_dvfs_ctrl_volt(1);
  391.                 break;
  392.             case DVFS_V3:
  393.                 idx = 2;  // spm_dvfs_ctrl_volt(2);
  394.                 break;
  395.             case DVFS_V4:
  396.                 idx = 3;  // spm_dvfs_ctrl_volt(3);
  397.                 break;
  398.             default:
  399.                 break;
  400.         }
  401.     }
  402.     else if((g_cpufreq_get_ptp_level >= 1) && (g_cpufreq_get_ptp_level <= 5))
  403.     {
  404.         switch (target_volt)
  405.         {
  406.             case DVFS_V0:
  407.                 idx = 0;  // spm_dvfs_ctrl_volt(0);
  408.                 break;
  409.             case DVFS_V1:
  410.                 idx = 1;  // spm_dvfs_ctrl_volt(1);
  411.                 break;
  412.             case DVFS_V2:
  413.                 idx = 2;  // spm_dvfs_ctrl_volt(2);
  414.                 break;
  415.             case DVFS_V3:
  416.                 idx = 3;  // spm_dvfs_ctrl_volt(3);
  417.                 break;
  418.             case DVFS_V4:
  419.                 idx = 4;  // spm_dvfs_ctrl_volt(4);
  420.                 break;
  421.             default:
  422.                 break;
  423.         }
  424.     }
  425.     else
  426.     {
  427.         switch (target_volt)
  428.         {
  429.             case DVFS_V1:
  430.                 idx = 0;  // spm_dvfs_ctrl_volt(0);
  431.                 break;
  432.             case DVFS_V2:
  433.                 idx = 1;  // spm_dvfs_ctrl_volt(1);
  434.                 break;
  435.             case DVFS_V3:
  436.                 idx = 2;  // spm_dvfs_ctrl_volt(2);
  437.                 break;
  438.             case DVFS_V4:
  439.                 idx = 3;  // spm_dvfs_ctrl_volt(3);
  440.                 break;
  441.             default:
  442.                 break;
  443.         }
  444.     }
  445.  
  446.     dprintk("mt_cpufreq_volt_to_pmic_wrap: current pmic wrap idx = %d\n", idx);
  447.     return idx;
  448. }
  449.  
  450. /* Set voltage because PTP-OD modified voltage table by PMIC wrapper */
  451. unsigned int mt_cpufreq_voltage_set_by_ptpod(unsigned int pmic_volt[], unsigned int array_size)
  452. {
  453.     int i, idx;
  454.     unsigned long flags;
  455.     unsigned int PMIC_WRAP_DVFS_WDATA_array[8] = {PMIC_WRAP_DVFS_WDATA0, PMIC_WRAP_DVFS_WDATA1, PMIC_WRAP_DVFS_WDATA2,
  456.                                                   PMIC_WRAP_DVFS_WDATA3, PMIC_WRAP_DVFS_WDATA4, PMIC_WRAP_DVFS_WDATA5,
  457.                                                   PMIC_WRAP_DVFS_WDATA6, PMIC_WRAP_DVFS_WDATA7};
  458.  
  459.     if(array_size > (sizeof(mt_cpufreq_pmic_volt)/4))
  460.     {
  461.         dprintk("mt_cpufreq_voltage_set_by_ptpod: ERROR!array_size is invalide, array_size = %d\n", array_size);
  462.     }
  463.    
  464.     spin_lock_irqsave(&mt_cpufreq_lock, flags);
  465.  
  466.     for (i = 0; i < array_size; i++)
  467.     {
  468.         mt65xx_reg_sync_writel(pmic_volt[i], PMIC_WRAP_DVFS_WDATA_array[i]);
  469.     }
  470.    
  471.     /* Check the mapping for DVFS voltage to pmic wrap voltage */
  472.     idx = mt_cpufreq_volt_to_pmic_wrap(g_cur_cpufreq_volt);
  473.     dprintk("Previous mt_cpufreq_pmic_volt[%d] = %x\n", idx, mt_cpufreq_pmic_volt[idx]);
  474.    
  475.     /* Check PTP-OD modify voltage UP or DOWN, because PTPOD maybe not change voltage all UP or DOWN. */
  476.     if(mt_cpufreq_pmic_volt[idx] > pmic_volt[idx])
  477.     {
  478.         mt_cpufreq_ptpod_voltage_down = true;
  479.     }
  480.     else if(mt_cpufreq_pmic_volt[idx] < pmic_volt[idx])
  481.     {
  482.         mt_cpufreq_ptpod_voltage_down = false;
  483.     }
  484.     else
  485.     {
  486.         for (i = 0; i < array_size; i++)
  487.         {
  488.             mt_cpufreq_pmic_volt[i] = pmic_volt[i];
  489.             dprintk("mt_cpufreq_pmic_volt[%d] = %x\n", i, mt_cpufreq_pmic_volt[i]);
  490.         }
  491.  
  492.         dprintk("mt_cpufreq_voltage_set_by_ptpod: pmic wrap voltage by PTP-OD was the same as previous!\n");
  493.         spin_unlock_irqrestore(&mt_cpufreq_lock, flags);
  494.         return 0;
  495.     }
  496.  
  497.     for (i = 0; i < array_size; i++)
  498.     {
  499.         mt_cpufreq_pmic_volt[i] = pmic_volt[i];
  500.         dprintk("mt_cpufreq_pmic_volt[%d] = %x\n", i, mt_cpufreq_pmic_volt[i]);
  501.     }
  502.    
  503.     dprintk("mt_cpufreq_voltage_set_by_ptpod: Set voltage directly by PTP-OD request! mt_cpufreq_ptpod_voltage_down = %d\n", mt_cpufreq_ptpod_voltage_down);
  504.  
  505.     /* If voltage down, need to consider DVS DOWN SW workaround. */
  506.     if(mt_cpufreq_ptpod_voltage_down == true)
  507.     {
  508.         #ifdef CPU_DVS_DOWN_SW_SOL
  509.         pmic_dvs_set_before_volt_change();
  510.         #endif
  511.  
  512.         mt_cpufreq_volt_set(g_cur_cpufreq_volt);
  513.  
  514.         #ifdef CPU_DVS_DOWN_SW_SOL
  515.         udelay(DVS_DOWN_SETTLE_TIME);
  516.         pmic_dvs_set_after_volt_settle();
  517.         #endif
  518.     }
  519.     else
  520.         mt_cpufreq_volt_set(g_cur_cpufreq_volt);
  521.  
  522.     spin_unlock_irqrestore(&mt_cpufreq_lock, flags);
  523.    
  524.     return 0;
  525. }
  526. EXPORT_SYMBOL(mt_cpufreq_voltage_set_by_ptpod);
  527.  
  528. /* Look for MAX frequency in number of DVS. */
  529. unsigned int mt_cpufreq_max_frequency_by_DVS(unsigned int num)
  530. {
  531.     int voltage_change_num = 0;
  532.     int i = 0;
  533.    
  534.     /* Assume mt6589_freqs_e1 voltage will be put in order, and freq will be put from high to low.*/
  535.     if(num == voltage_change_num)
  536.     {
  537.         xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "PTPOD0:num = %d, frequency= %d\n", num, mt_cpu_freqs[0].cpufreq_khz);
  538.         return mt_cpu_freqs[0].cpufreq_khz;
  539.     }
  540.    
  541.     for (i = 1; i < mt_cpu_freqs_num; i++)
  542.     {
  543.         if(mt_cpu_freqs[i].cpufreq_volt != mt_cpu_freqs[i-1].cpufreq_volt)
  544.             voltage_change_num++;
  545.        
  546.         if(num == voltage_change_num)
  547.         {
  548.             xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "PTPOD1:num = %d, frequency= %d\n", num, mt_cpu_freqs[i].cpufreq_khz);
  549.             return mt_cpu_freqs[i].cpufreq_khz;
  550.         }
  551.     }
  552.  
  553.     xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "PTPOD2:num = %d, NOT found! return 0!\n", num);
  554.     return 0;
  555. }
  556. EXPORT_SYMBOL(mt_cpufreq_max_frequency_by_DVS);
  557.  
  558.  
  559. static void mt_setup_power_table(int num)
  560. {
  561.     int i = 0, j = 0, p_dynamic = 0, p_leakage = 0, freq_ratio = 0, volt_square_ratio = 0;
  562.     struct mt_cpu_power_info temp_power_info;
  563.  
  564.     dprintk("P_MCU_D = %d\n", P_MCU_D);  
  565.  
  566.     dprintk("P_CA7_D_1_CORE = %d, P_CA7_D_2_CORE = %d, P_CA7_D_3_CORE = %d, P_CA7_D_4_CORE = %d\n",
  567.              P_CA7_D_1_CORE, P_CA7_D_2_CORE, P_CA7_D_3_CORE, P_CA7_D_4_CORE);
  568.  
  569.     dprintk("P_TOTAL_CORE_L = %d, P_EACH_CORE_L = %d\n",
  570.              P_TOTAL_CORE_L, P_EACH_CORE_L);
  571.  
  572.     dprintk("A_1_CORE = %d, A_2_CORE = %d, A_3_CORE = %d, A_4_CORE = %d\n",
  573.              A_1_CORE, A_2_CORE, A_3_CORE, A_4_CORE);
  574.  
  575.     mt_cpu_power = kzalloc((num * 4) * sizeof(struct mt_cpu_power_info), GFP_KERNEL);
  576.  
  577.     for (i = 0; i < num; i++)
  578.     {
  579.         volt_square_ratio = (((mt_cpu_freqs[i].cpufreq_volt * 100) / 1150) * ((mt_cpu_freqs[i].cpufreq_volt * 100) / 1150)) / 100;
  580.         freq_ratio = (mt_cpu_freqs[i].cpufreq_khz / 1300);
  581.         dprintk("freq_ratio = %d, volt_square_ratio %d\n", freq_ratio, volt_square_ratio);
  582.  
  583.         // 1 core
  584.         p_dynamic = (((A_1_CORE * freq_ratio) / 1000) * volt_square_ratio) / 100;
  585.         p_leakage = ((P_TOTAL_CORE_L * ((mt_cpu_freqs[i].cpufreq_volt * 100) / 1150)) / 100) - 3 * P_EACH_CORE_L;
  586.         dprintk("p_dynamic = %d, p_leakage = %d\n", p_dynamic, p_leakage);
  587.  
  588.         mt_cpu_power[i * 4 + 0].cpufreq_ncpu = 1;
  589.         mt_cpu_power[i * 4 + 0].cpufreq_khz = mt_cpu_freqs[i].cpufreq_khz;
  590.         mt_cpu_power[i * 4 + 0].cpufreq_power = p_dynamic + p_leakage;
  591.         xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "mt_cpu_power[%d]: cpufreq_ncpu = %d, cpufreq_khz = %d, cpufreq_power = %d\n", (i * 4 + 0),
  592.                                                      mt_cpu_power[(i * 4 + 0)].cpufreq_ncpu, mt_cpu_power[(i * 4 + 0)].cpufreq_khz, mt_cpu_power[(i * 4 + 0)].cpufreq_power);
  593.  
  594.         // 2 core
  595.         p_dynamic = (((A_2_CORE * freq_ratio) / 1000) * volt_square_ratio) / 100;
  596.         p_leakage = ((P_TOTAL_CORE_L * ((mt_cpu_freqs[i].cpufreq_volt * 100) / 1150)) / 100) - 2 * P_EACH_CORE_L;
  597.         dprintk("p_dynamic = %d, p_leakage = %d\n", p_dynamic, p_leakage);
  598.  
  599.         mt_cpu_power[i * 4 + 1].cpufreq_ncpu = 2;
  600.         mt_cpu_power[i * 4 + 1].cpufreq_khz = mt_cpu_freqs[i].cpufreq_khz;
  601.         mt_cpu_power[i * 4 + 1].cpufreq_power = p_dynamic + p_leakage;
  602.         xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "mt_cpu_power[%d]: cpufreq_ncpu = %d, cpufreq_khz = %d, cpufreq_power = %d\n", (i * 4 + 1),
  603.                                                      mt_cpu_power[(i * 4 + 1)].cpufreq_ncpu, mt_cpu_power[(i * 4 + 1)].cpufreq_khz, mt_cpu_power[(i * 4 + 1)].cpufreq_power);
  604.  
  605.         // 3 core
  606.         p_dynamic = (((A_3_CORE * freq_ratio) / 1000) * volt_square_ratio) / 100;
  607.         p_leakage = ((P_TOTAL_CORE_L * ((mt_cpu_freqs[i].cpufreq_volt * 100) / 1150)) / 100) - 1 * P_EACH_CORE_L;
  608.         dprintk("p_dynamic = %d, p_leakage = %d\n", p_dynamic, p_leakage);
  609.  
  610.         mt_cpu_power[i * 4 + 2].cpufreq_ncpu = 3;
  611.         mt_cpu_power[i * 4 + 2].cpufreq_khz = mt_cpu_freqs[i].cpufreq_khz;
  612.         mt_cpu_power[i * 4 + 2].cpufreq_power = p_dynamic + p_leakage;
  613.         xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "mt_cpu_power[%d]: cpufreq_ncpu = %d, cpufreq_khz = %d, cpufreq_power = %d\n", (i * 4 + 2),
  614.                                                      mt_cpu_power[(i * 4 + 2)].cpufreq_ncpu, mt_cpu_power[(i * 4 + 2)].cpufreq_khz, mt_cpu_power[(i * 4 + 2)].cpufreq_power);
  615.  
  616.         // 4 core
  617.         p_dynamic = (((A_4_CORE * freq_ratio) / 1000) * volt_square_ratio) / 100;
  618.         p_leakage = (P_TOTAL_CORE_L * ((mt_cpu_freqs[i].cpufreq_volt * 100) / 1150)) / 100;
  619.         dprintk("p_dynamic = %d, p_leakage = %d\n", p_dynamic, p_leakage);
  620.  
  621.         mt_cpu_power[i * 4 + 3].cpufreq_ncpu = 4;
  622.         mt_cpu_power[i * 4 + 3].cpufreq_khz = mt_cpu_freqs[i].cpufreq_khz;
  623.         mt_cpu_power[i * 4 + 3].cpufreq_power = p_dynamic + p_leakage;
  624.         xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "mt_cpu_power[%d]: cpufreq_ncpu = %d, cpufreq_khz = %d, cpufreq_power = %d\n", (i * 4 + 3),
  625.                                                      mt_cpu_power[(i * 4 + 3)].cpufreq_ncpu, mt_cpu_power[(i * 4 + 3)].cpufreq_khz, mt_cpu_power[(i * 4 + 3)].cpufreq_power);
  626.     }
  627.  
  628.     for (i = (num * 4 - 1); i > 0; i--)
  629.     {
  630.         for (j = 1; j <= i; j++)
  631.         {
  632.             if (mt_cpu_power[j - 1].cpufreq_power < mt_cpu_power[j].cpufreq_power)
  633.             {
  634.                 temp_power_info.cpufreq_khz = mt_cpu_power[j - 1].cpufreq_khz;
  635.                 temp_power_info.cpufreq_ncpu = mt_cpu_power[j - 1].cpufreq_ncpu;
  636.                 temp_power_info.cpufreq_power = mt_cpu_power[j - 1].cpufreq_power;
  637.  
  638.                 mt_cpu_power[j - 1].cpufreq_khz = mt_cpu_power[j].cpufreq_khz;
  639.                 mt_cpu_power[j - 1].cpufreq_ncpu = mt_cpu_power[j].cpufreq_ncpu;
  640.                 mt_cpu_power[j - 1].cpufreq_power = mt_cpu_power[j].cpufreq_power;
  641.  
  642.                 mt_cpu_power[j].cpufreq_khz = temp_power_info.cpufreq_khz;
  643.                 mt_cpu_power[j].cpufreq_ncpu = temp_power_info.cpufreq_ncpu;
  644.                 mt_cpu_power[j].cpufreq_power = temp_power_info.cpufreq_power;
  645.             }
  646.         }
  647.     }
  648.  
  649.     for (i = 0; i < (num * 4); i++)
  650.     {
  651.         dprintk("mt_cpu_power[%d].cpufreq_khz = %d, ", i, mt_cpu_power[i].cpufreq_khz);
  652.         dprintk("mt_cpu_power[%d].cpufreq_ncpu = %d, ", i, mt_cpu_power[i].cpufreq_ncpu);
  653.         dprintk("mt_cpu_power[%d].cpufreq_power = %d\n", i, mt_cpu_power[i].cpufreq_power);
  654.     }
  655.  
  656.     #ifdef CONFIG_THERMAL
  657.         mtk_cpufreq_register(mt_cpu_power, (num * 4));
  658.     #endif
  659. }
  660.  
  661. /***********************************************
  662. * register frequency table to cpufreq subsystem
  663. ************************************************/
  664. static int mt_setup_freqs_table(struct cpufreq_policy *policy, struct mt_cpu_freq_info *freqs, int num)
  665. {
  666.     struct cpufreq_frequency_table *table;
  667.     int i, ret;
  668.  
  669.     table = kzalloc((num + 1) * sizeof(*table), GFP_KERNEL);
  670.     if (table == NULL)
  671.         return -ENOMEM;
  672.  
  673.     for (i = 0; i < num; i++) {
  674.         table[i].index = i;
  675.         table[i].frequency = freqs[i].cpufreq_khz;
  676.     }
  677.     table[num].frequency = i;
  678.     table[num].frequency = CPUFREQ_TABLE_END;
  679.  
  680.     mt_cpu_freqs = freqs;
  681.     mt_cpu_freqs_num = num;
  682.     mt_cpu_freqs_table = table;
  683.  
  684.     ret = cpufreq_frequency_table_cpuinfo(policy, table);
  685.     if (!ret)
  686.         cpufreq_frequency_table_get_attr(mt_cpu_freqs_table, policy->cpu);
  687.  
  688.     if (mt_cpu_power == NULL)
  689.         mt_setup_power_table(num);
  690.  
  691.     return 0;
  692. }
  693.  
  694. /*****************************
  695. * set CPU DVFS status
  696. ******************************/
  697. int mt_cpufreq_state_set(int enabled)
  698. {
  699.     if (enabled)
  700.     {
  701.         if (!mt_cpufreq_pause)
  702.         {
  703.             xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "cpufreq already enabled\n");
  704.             return 0;
  705.         }
  706.  
  707.         /*************
  708.         * enable DVFS
  709.         **************/
  710.         g_dvfs_disable_count--;
  711.         xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "enable DVFS: g_dvfs_disable_count = %d\n", g_dvfs_disable_count);
  712.  
  713.         /***********************************************
  714.         * enable DVFS if no any module still disable it
  715.         ************************************************/
  716.         if (g_dvfs_disable_count <= 0)
  717.         {
  718.             mt_cpufreq_pause = false;
  719.         }
  720.         else
  721.         {
  722.             xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "someone still disable cpufreq, cannot enable it\n");
  723.         }
  724.     }
  725.     else
  726.     {
  727.         /**************
  728.         * disable DVFS
  729.         ***************/
  730.         g_dvfs_disable_count++;
  731.         xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "disable DVFS: g_dvfs_disable_count = %d\n", g_dvfs_disable_count);
  732.  
  733.         if (mt_cpufreq_pause)
  734.         {
  735.             xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "cpufreq already disabled\n");
  736.             return 0;
  737.         }
  738.  
  739.         mt_cpufreq_pause = true;
  740.     }
  741.  
  742.     return 0;
  743. }
  744. EXPORT_SYMBOL(mt_cpufreq_state_set);
  745.  
  746. static int mt_cpufreq_verify(struct cpufreq_policy *policy)
  747. {
  748.     dprintk("call mt_cpufreq_verify!\n");
  749.     return cpufreq_frequency_table_verify(policy, mt_cpu_freqs_table);
  750. }
  751.  
  752. static unsigned int mt_cpufreq_get(unsigned int cpu)
  753. {
  754.     dprintk("call mt_cpufreq_get: %d!\n", g_cur_freq);
  755.     return g_cur_freq;
  756. }
  757.  
  758. static void mt_cpu_clock_switch(unsigned int sel)
  759. {
  760.     unsigned int ckmuxsel = 0;
  761.  
  762.     ckmuxsel = DRV_Reg32(TOP_CKMUXSEL) & ~0xC;
  763.  
  764.     switch (sel)
  765.     {
  766.         case TOP_CKMUXSEL_CLKSQ:
  767.             mt65xx_reg_sync_writel((ckmuxsel | 0x00), TOP_CKMUXSEL);
  768.             break;
  769.         case TOP_CKMUXSEL_ARMPLL:
  770.             mt65xx_reg_sync_writel((ckmuxsel | 0x04), TOP_CKMUXSEL);
  771.             break;
  772.         case TOP_CKMUXSEL_MAINPLL:
  773.             mt65xx_reg_sync_writel((ckmuxsel | 0x08), TOP_CKMUXSEL);
  774.             break;
  775.         case TOP_CKMUXSEL_MMPLL:
  776.             mt65xx_reg_sync_writel((ckmuxsel | 0x0C), TOP_CKMUXSEL);
  777.             break;
  778.         default:
  779.             break;
  780.     }
  781. }
  782.  
  783. /* Need sync with mt_cpufreq_volt_to_pmic_wrap(), mt_cpufreq_pdrv_probe() */
  784. static void mt_cpufreq_volt_set(unsigned int target_volt)
  785. {
  786.     if(g_cpufreq_get_ptp_level == 0)
  787.     {
  788.         switch (target_volt)
  789.         {
  790.             case DVFS_V1:
  791.                 dprintk("switch to DVS0: %d mV\n", DVFS_V1);
  792.                 spm_dvfs_ctrl_volt(0);
  793.                 break;
  794.             case DVFS_V2:
  795.                 dprintk("switch to DVS1: %d mV\n", DVFS_V2);
  796.                 spm_dvfs_ctrl_volt(1);
  797.                 break;
  798.             case DVFS_V3:
  799.                 dprintk("switch to DVS2: %d mV\n", DVFS_V3);
  800.                 spm_dvfs_ctrl_volt(2);
  801.                 break;
  802.             case DVFS_V4:
  803.                 dprintk("switch to DVS3: %d mV\n", DVFS_V4);
  804.                 spm_dvfs_ctrl_volt(3);
  805.                 break;
  806.             default:
  807.                 break;
  808.         }
  809.     }
  810.     else if((g_cpufreq_get_ptp_level >= 1) && (g_cpufreq_get_ptp_level <= 5))
  811.     {
  812.         switch (target_volt)
  813.         {
  814.             case DVFS_V0:
  815.                 dprintk("switch to DVS0: %d mV\n", DVFS_V0);
  816.                 spm_dvfs_ctrl_volt(0);
  817.                 break;
  818.             case DVFS_V1:
  819.                 dprintk("switch to DVS1: %d mV\n", DVFS_V1);
  820.                 spm_dvfs_ctrl_volt(1);
  821.                 break;
  822.             case DVFS_V2:
  823.                 dprintk("switch to DVS2: %d mV\n", DVFS_V2);
  824.                 spm_dvfs_ctrl_volt(2);
  825.                 break;
  826.             case DVFS_V3:
  827.                 dprintk("switch to DVS3: %d mV\n", DVFS_V3);
  828.                 spm_dvfs_ctrl_volt(3);
  829.                 break;
  830.             case DVFS_V4:
  831.                 dprintk("switch to DVS4: %d mV\n", DVFS_V4);
  832.                 spm_dvfs_ctrl_volt(4);
  833.                 break;
  834.             default:
  835.                 break;
  836.         }
  837.     }
  838.     else
  839.     {
  840.         switch (target_volt)
  841.         {
  842.             case DVFS_V1:
  843.                 dprintk("switch to DVS0: %d mV\n", DVFS_V1);
  844.                 spm_dvfs_ctrl_volt(0);
  845.                 break;
  846.             case DVFS_V2:
  847.                 dprintk("switch to DVS1: %d mV\n", DVFS_V2);
  848.                 spm_dvfs_ctrl_volt(1);
  849.                 break;
  850.             case DVFS_V3:
  851.                 dprintk("switch to DVS2: %d mV\n", DVFS_V3);
  852.                 spm_dvfs_ctrl_volt(2);
  853.                 break;
  854.             case DVFS_V4:
  855.                 dprintk("switch to DVS3: %d mV\n", DVFS_V4);
  856.                 spm_dvfs_ctrl_volt(3);
  857.                 break;
  858.             default:
  859.                 break;
  860.         }
  861.     }
  862. }
  863.  
  864. /*****************************************
  865. * frequency ramp up and ramp down handler
  866. ******************************************/
  867. /***********************************************************
  868. * [note]
  869. * 1. frequency ramp up need to wait voltage settle
  870. * 2. frequency ramp down do not need to wait voltage settle
  871. ************************************************************/
  872. static void mt_cpufreq_set(unsigned int freq_old, unsigned int freq_new, unsigned int target_volt)
  873. {
  874.     unsigned int armpll = 0;
  875.  
  876.     if (freq_new >= 1001000)
  877.     {
  878.         armpll = 0x8009A000;
  879.         armpll = armpll + ((freq_new - 1001000) / 13000) * 0x2000;
  880.     }
  881.     else if (freq_new >= 520000)
  882.     {
  883.         armpll = 0x810A0000;
  884.         armpll = armpll + ((freq_new - 520000) / 6500) * 0x2000;
  885.     }
  886.     else
  887.     {
  888.         armpll = 0x820A0000;
  889.         armpll = armpll + ((freq_new - 260000) / 3250) * 0x2000;
  890.     }
  891.  
  892.     enable_pll(MAINPLL, "CPU_DVFS");
  893.     if (freq_new > freq_old)
  894.     {
  895.         #ifdef CPU_DVS_DOWN_SW_SOL
  896.         if(mt_cpufreq_max_freq_overdrive == true) /* if chip support frequency > 1.2GHz (DVFS_F1) */
  897.         {
  898.             if(freq_new == mt_cpu_freqs[0].cpufreq_khz) /* if frequency > 1.2GHz (DVFS_F1) */
  899.             {
  900.                 pmic_dvs_into_highest_level_set_before_volt_change();
  901.             }
  902.         }
  903.         #endif
  904.  
  905.         #ifdef MT_BUCK_ADJUST
  906.         mt_cpufreq_volt_set(target_volt);
  907.         udelay(PMIC_SETTLE_TIME);
  908.         #endif
  909.  
  910.         mt65xx_reg_sync_writel(0x0A, TOP_CKDIV1);
  911.         mt_cpu_clock_switch(TOP_CKMUXSEL_MAINPLL);
  912.  
  913.         mt65xx_reg_sync_writel(armpll, ARMPLL_CON1);
  914.  
  915.         mb();
  916.         udelay(PLL_SETTLE_TIME);
  917.  
  918.         mt_cpu_clock_switch(TOP_CKMUXSEL_ARMPLL);
  919.         mt65xx_reg_sync_writel(0x00, TOP_CKDIV1);
  920.     }
  921.     else
  922.     {
  923.         mt65xx_reg_sync_writel(0x0A, TOP_CKDIV1);
  924.         mt_cpu_clock_switch(TOP_CKMUXSEL_MAINPLL);
  925.  
  926.         mt65xx_reg_sync_writel(armpll, ARMPLL_CON1);
  927.  
  928.         mb();
  929.         udelay(PLL_SETTLE_TIME);
  930.  
  931.         mt_cpu_clock_switch(TOP_CKMUXSEL_ARMPLL);
  932.         mt65xx_reg_sync_writel(0x00, TOP_CKDIV1);
  933.  
  934.         #ifdef CPU_DVS_DOWN_SW_SOL
  935.         pmic_dvs_set_before_volt_change();
  936.         #endif
  937.        
  938.         #ifdef MT_BUCK_ADJUST
  939.         mt_cpufreq_volt_set(target_volt);
  940.         #endif
  941.  
  942.         #ifdef CPU_DVS_DOWN_SW_SOL
  943.         udelay(DVS_DOWN_SETTLE_TIME);
  944.         pmic_dvs_set_after_volt_settle();
  945.         #endif
  946.     }
  947.     disable_pll(MAINPLL, "CPU_DVFS");
  948.  
  949.     g_cur_freq = freq_new;
  950.     g_cur_cpufreq_volt = target_volt;
  951.  
  952.     dprintk("ARMPLL_CON0 = 0x%x, ARMPLL_CON1 = 0x%x, g_cur_freq = %d\n", DRV_Reg32(ARMPLL_CON0), DRV_Reg32(ARMPLL_CON1), g_cur_freq);
  953. }
  954.  
  955. /**************************************
  956. * check if maximum frequency is needed
  957. ***************************************/
  958. static int mt_cpufreq_keep_max_freq(unsigned int freq_old, unsigned int freq_new)
  959. {
  960.     if (mt_cpufreq_pause)
  961.         return 1;
  962.  
  963.     /* check if system is going to ramp down */
  964.     if (freq_new < freq_old)
  965.         g_ramp_down_count++;
  966.     else
  967.         g_ramp_down_count = 0;
  968.  
  969.     if (g_ramp_down_count < RAMP_DOWN_TIMES)
  970.         return 1;
  971.  
  972.     return 0;
  973. }
  974.  
  975. #ifdef MT_DVFS_RANDOM_TEST
  976. static int mt_cpufreq_idx_get(int num)
  977. {
  978.     int random = 0, mult = 0, idx;
  979.     random = jiffies & 0xF;
  980.  
  981.     while (1)
  982.     {
  983.         if ((mult * num) >= random)
  984.         {
  985.             idx = (mult * num) - random;
  986.             break;
  987.         }
  988.         mult++;
  989.     }
  990.     return idx;
  991. }
  992. #endif
  993.  
  994. static unsigned int mt_thermal_limited_verify(unsigned int target_freq)
  995. {
  996.     int i = 0, index = 0;
  997.  
  998.     for (i = 0; i < (mt_cpu_freqs_num * 4); i++)
  999.     {
  1000.         if (mt_cpu_power[i].cpufreq_ncpu == g_limited_max_ncpu && mt_cpu_power[i].cpufreq_khz == g_limited_max_freq)
  1001.         {
  1002.             index = i;
  1003.             break;
  1004.         }
  1005.     }
  1006.  
  1007.     for (index = i; index < (mt_cpu_freqs_num * 4); index++)
  1008.     {
  1009.         if (mt_cpu_power[i].cpufreq_ncpu == num_online_cpus())
  1010.         {
  1011.             if (target_freq >= mt_cpu_power[i].cpufreq_khz)
  1012.             {
  1013.                 dprintk("target_freq = %d, ncpu = %d\n", mt_cpu_power[i].cpufreq_khz, num_online_cpus());
  1014.                 target_freq = mt_cpu_power[i].cpufreq_khz;
  1015.                 break;
  1016.             }
  1017.         }
  1018.     }
  1019.  
  1020.     return target_freq;
  1021. }
  1022.  
  1023. /**********************************
  1024. * cpufreq target callback function
  1025. ***********************************/
  1026. /*************************************************
  1027. * [note]
  1028. * 1. handle frequency change request
  1029. * 2. call mt_cpufreq_set to set target frequency
  1030. **************************************************/
  1031. static int mt_cpufreq_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation)
  1032. {
  1033.     int i, idx;
  1034.     unsigned int cpu;
  1035.     unsigned long flags;
  1036.  
  1037.     struct mt_cpu_freq_info next;
  1038.     struct cpufreq_freqs freqs;
  1039.  
  1040.     if (!mt_cpufreq_ready)
  1041.         return -ENOSYS;
  1042.  
  1043.     if (policy->cpu >= num_possible_cpus())
  1044.         return -EINVAL;
  1045.  
  1046.     /******************************
  1047.     * look up the target frequency
  1048.     *******************************/
  1049.     if (cpufreq_frequency_table_target(policy, mt_cpu_freqs_table, target_freq, relation, &idx))
  1050.     {
  1051.         return -EINVAL;
  1052.     }
  1053.  
  1054.     #ifdef MT_DVFS_RANDOM_TEST
  1055.     idx = mt_cpufreq_idx_get(4);
  1056.     #endif
  1057.  
  1058.     if(g_cpufreq_get_ptp_level == 0)
  1059.         next.cpufreq_khz = mt6589_freqs_e1[idx].cpufreq_khz;
  1060.     else if(g_cpufreq_get_ptp_level == 1)
  1061.         next.cpufreq_khz = mt6589_freqs_e1_4[idx].cpufreq_khz;
  1062.     else if(g_cpufreq_get_ptp_level == 2)
  1063.         next.cpufreq_khz = mt6589_freqs_e1_3[idx].cpufreq_khz;
  1064.     else if(g_cpufreq_get_ptp_level == 3)
  1065.         next.cpufreq_khz = mt6589_freqs_e1_2[idx].cpufreq_khz;
  1066.     else if(g_cpufreq_get_ptp_level == 4)
  1067.         next.cpufreq_khz = mt6589_freqs_e1_1[idx].cpufreq_khz;
  1068.     else if(g_cpufreq_get_ptp_level == 5)
  1069.         next.cpufreq_khz = mt6589_freqs_e1_0[idx].cpufreq_khz;
  1070.     else
  1071.         next.cpufreq_khz = mt6589_freqs_e1[idx].cpufreq_khz;
  1072.  
  1073.     #ifdef MT_DVFS_RANDOM_TEST
  1074.     dprintk("idx = %d, freqs.old = %d, freqs.new = %d\n", idx, policy->cur, next.cpufreq_khz);
  1075.     #endif
  1076.  
  1077.     freqs.old = policy->cur;
  1078.     freqs.new = next.cpufreq_khz;
  1079.     freqs.cpu = policy->cpu;
  1080.  
  1081.     #ifndef MT_DVFS_RANDOM_TEST
  1082.     if (mt_cpufreq_keep_max_freq(freqs.old, freqs.new))
  1083.     {
  1084.        
  1085.     //<<EricHsieh,2013/5/20,Using DVFS at early suspend mode        
  1086.     #ifdef MIN_FREQ_EARLY_SUSPEND
  1087.         if(mt_cpufreq_limit_min_freq_early_suspend == true)
  1088.             freqs.new = early_suspnd_freq;
  1089.         else
  1090.             freqs.new = policy->max;
  1091.     #else
  1092.         freqs.new = policy->max;
  1093.     #endif
  1094.     //>>EricHsieh,2013/5/20,Using DVFS at early suspend mode
  1095.     }
  1096.  
  1097.     /************************************************
  1098.     * DVFS keep at 1.2GHz in earlysuspend when max freq overdrive.
  1099.     *************************************************/
  1100.     if(mt_cpufreq_limit_max_freq_early_suspend == true)
  1101.     {
  1102.         freqs.new = DVFS_F0_4 ;
  1103.         dprintk("mt_cpufreq_limit_max_freq_early_suspend, freqs.new = %d\n", freqs.new);
  1104.     }
  1105.  
  1106. #ifdef MIN_FREQ_EARLY_SUSPEND
  1107.     if(mt_cpufreq_limit_min_freq_early_suspend == true)
  1108.     {
  1109.         freqs.new = early_suspnd_freq;
  1110.         dprintk("mt_cpufreq_limit_max_freq_early_suspend, freqs.new = %d\n", freqs.new);
  1111.     }
  1112. #endif 
  1113.    
  1114.     freqs.new = mt_thermal_limited_verify(freqs.new);
  1115.  
  1116.     if (freqs.new < g_limited_min_freq)
  1117.     {
  1118.         dprintk("cannot switch CPU frequency to %d Mhz due to voltage limitation\n", g_limited_min_freq / 1000);
  1119.         freqs.new = g_limited_min_freq;
  1120.     }
  1121.     #endif
  1122.  
  1123.     /************************************************
  1124.     * DVFS keep at 1001Mhz/1.15V when PTPOD initial
  1125.     *************************************************/
  1126.     if (mt_cpufreq_ptpod_disable)
  1127.     {
  1128.         freqs.new = DVFS_F2;
  1129.         dprintk("PTPOD, freqs.new = %d\n", freqs.new);
  1130.     }
  1131.  
  1132.     /************************************************
  1133.     * target frequency == existing frequency, skip it
  1134.     *************************************************/
  1135.     if (freqs.old == freqs.new)
  1136.     {
  1137.         dprintk("CPU frequency from %d MHz to %d MHz (skipped) due to same frequency\n", freqs.old / 1000, freqs.new / 1000);
  1138.         return 0;
  1139.     }
  1140.  
  1141.     /**************************************
  1142.     * search for the corresponding voltage
  1143.     ***************************************/
  1144.     next.cpufreq_volt = 0;
  1145.  
  1146.     for (i = 0; i < mt_cpu_freqs_num; i++)
  1147.     {
  1148.         dprintk("freqs.new = %d, mt_cpu_freqs[%d].cpufreq_khz = %d\n", freqs.new, i, mt_cpu_freqs[i].cpufreq_khz);
  1149.         if (freqs.new == mt_cpu_freqs[i].cpufreq_khz)
  1150.         {
  1151.             next.cpufreq_volt = mt_cpu_freqs[i].cpufreq_volt;
  1152.             dprintk("next.cpufreq_volt = %d, mt_cpu_freqs[%d].cpufreq_volt = %d\n", next.cpufreq_volt, i, mt_cpu_freqs[i].cpufreq_volt);
  1153.             break;
  1154.         }
  1155.     }
  1156.  
  1157.     if (next.cpufreq_volt == 0)
  1158.     {
  1159.         dprintk("Error!! Cannot find corresponding voltage at %d Mhz\n", freqs.new / 1000);
  1160.         return 0;
  1161.     }
  1162.  
  1163.     for_each_online_cpu(cpu)
  1164.     {
  1165.         freqs.cpu = cpu;
  1166.         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
  1167.     }
  1168.  
  1169.     spin_lock_irqsave(&mt_cpufreq_lock, flags);
  1170.  
  1171.     /******************************
  1172.     * set to the target freeuency
  1173.     *******************************/
  1174.     mt_cpufreq_set(freqs.old, freqs.new, next.cpufreq_volt);
  1175.  
  1176.     spin_unlock_irqrestore(&mt_cpufreq_lock, flags);
  1177.  
  1178.     for_each_online_cpu(cpu)
  1179.     {
  1180.         freqs.cpu = cpu;
  1181.         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
  1182.     }
  1183.  
  1184.     return 0;
  1185. }
  1186.  
  1187. /*********************************************************
  1188. * set up frequency table and register to cpufreq subsystem
  1189. **********************************************************/
  1190. static int mt_cpufreq_init(struct cpufreq_policy *policy)
  1191. {
  1192.     int ret = -EINVAL;
  1193.  
  1194.     if (policy->cpu >= num_possible_cpus())
  1195.         return -EINVAL;
  1196.  
  1197.     policy->shared_type = CPUFREQ_SHARED_TYPE_ANY;
  1198.     cpumask_setall(policy->cpus);
  1199.  
  1200.     /*******************************************************
  1201.     * 1 us, assumed, will be overwrited by min_sampling_rate
  1202.     ********************************************************/
  1203.     policy->cpuinfo.transition_latency = 1000;
  1204.  
  1205.     /*********************************************
  1206.     * set default policy and cpuinfo, unit : Khz
  1207.     **********************************************/
  1208.     policy->cpuinfo.max_freq = g_max_freq_by_ptp;
  1209.     policy->cpuinfo.min_freq = DVFS_F4;
  1210.  
  1211.     policy->cur = DVFS_F2;
  1212.     policy->max = g_max_freq_by_ptp;
  1213.     policy->min = DVFS_F4;
  1214.  
  1215.     if(g_cpufreq_get_ptp_level == 0)
  1216.         ret = mt_setup_freqs_table(policy, ARRAY_AND_SIZE(mt6589_freqs_e1));
  1217.     else if(g_cpufreq_get_ptp_level == 1)
  1218.         ret = mt_setup_freqs_table(policy, ARRAY_AND_SIZE(mt6589_freqs_e1_4));
  1219.     else if(g_cpufreq_get_ptp_level == 2)
  1220.         ret = mt_setup_freqs_table(policy, ARRAY_AND_SIZE(mt6589_freqs_e1_3));
  1221.     else if(g_cpufreq_get_ptp_level == 3)
  1222.         ret = mt_setup_freqs_table(policy, ARRAY_AND_SIZE(mt6589_freqs_e1_2));
  1223.     else if(g_cpufreq_get_ptp_level == 4)
  1224.         ret = mt_setup_freqs_table(policy, ARRAY_AND_SIZE(mt6589_freqs_e1_1));
  1225.     else if(g_cpufreq_get_ptp_level == 5)
  1226.         ret = mt_setup_freqs_table(policy, ARRAY_AND_SIZE(mt6589_freqs_e1_0));
  1227.     else
  1228.         ret = mt_setup_freqs_table(policy, ARRAY_AND_SIZE(mt6589_freqs_e1));
  1229.    
  1230.     if (ret) {
  1231.         xlog_printk(ANDROID_LOG_ERROR, "Power/DVFS", "failed to setup frequency table\n");
  1232.         return ret;
  1233.     }
  1234.  
  1235.     return 0;
  1236. }
  1237.  
  1238. static struct freq_attr *mt_cpufreq_attr[] = {
  1239.     &cpufreq_freq_attr_scaling_available_freqs,
  1240.     NULL,
  1241. };
  1242.  
  1243. static struct cpufreq_driver mt_cpufreq_driver = {
  1244.     .verify = mt_cpufreq_verify,
  1245.     .target = mt_cpufreq_target,
  1246.     .init   = mt_cpufreq_init,
  1247.     .get    = mt_cpufreq_get,
  1248.     .name   = "mt-cpufreq",
  1249.     .attr   = mt_cpufreq_attr,
  1250. };
  1251.  
  1252. /*********************************
  1253. * early suspend callback function
  1254. **********************************/
  1255. void mt_cpufreq_early_suspend(struct early_suspend *h)
  1256. {
  1257.     #ifndef MT_DVFS_RANDOM_TEST
  1258.  
  1259. //<<EricHsieh,2013/5/20,Using DVFS at early suspend mode
  1260. #ifdef MIN_FREQ_EARLY_SUSPEND
  1261. if(eraly_suspend_dvfs){
  1262.         mt_cpufreq_state_set(1);
  1263. }
  1264. else{
  1265.         mt_cpufreq_state_set(0);
  1266.         mt_cpufreq_limit_min_freq_early_suspend = true;
  1267.         mt_cpufreq_limit_min_freq_by_early_suspend();
  1268. }
  1269. #else
  1270.     mt_cpufreq_state_set(0);
  1271.     if(mt_cpufreq_max_freq_overdrive == true)
  1272.     {
  1273.         mt_cpufreq_limit_max_freq_early_suspend = true;
  1274.         mt_cpufreq_limit_max_freq_by_early_suspend();
  1275.     }
  1276. #endif
  1277. //>>EricHsieh,2013/5/20,Using DVFS at early suspend mode
  1278.  
  1279.     #endif
  1280.  
  1281.     return;
  1282. }
  1283.  
  1284. /*******************************
  1285. * late resume callback function
  1286. ********************************/
  1287. void mt_cpufreq_late_resume(struct early_suspend *h)
  1288. {
  1289.     #ifndef MT_DVFS_RANDOM_TEST
  1290.  
  1291.     if(mt_cpufreq_max_freq_overdrive == true)
  1292.     {
  1293.         mt_cpufreq_limit_max_freq_early_suspend = false;
  1294.     }
  1295.    
  1296. #ifdef MIN_FREQ_EARLY_SUSPEND
  1297.     mt_cpufreq_limit_min_freq_early_suspend = false;    //<<EricHsieh,2013/5/20,Using DVFS at early suspend mode
  1298. #endif     
  1299.     mt_cpufreq_state_set(1);
  1300.  
  1301.     #endif
  1302.  
  1303.     return;
  1304. }
  1305.  
  1306. /************************************************
  1307. * API to switch back default voltage setting for PTPOD disabled
  1308. *************************************************/
  1309. void mt_cpufreq_return_default_DVS_by_ptpod(void)
  1310. {
  1311.     if(g_cpufreq_get_ptp_level == 0)
  1312.     {
  1313.         mt65xx_reg_sync_writel(0x50, PMIC_WRAP_DVFS_WDATA0); // 1.20V VPROC
  1314.         mt65xx_reg_sync_writel(0x48, PMIC_WRAP_DVFS_WDATA1); // 1.15V VPROC
  1315.         mt65xx_reg_sync_writel(0x38, PMIC_WRAP_DVFS_WDATA2); // 1.05V VPROC
  1316.         mt65xx_reg_sync_writel(0x28, PMIC_WRAP_DVFS_WDATA3); // 0.95V VPROC
  1317.         mt65xx_reg_sync_writel(0x18, PMIC_WRAP_DVFS_WDATA4); // 0.85V VPROC
  1318.  
  1319.         /* For PTP-OD */
  1320.         mt_cpufreq_pmic_volt[0] = 0x50;
  1321.         mt_cpufreq_pmic_volt[1] = 0x48;
  1322.         mt_cpufreq_pmic_volt[2] = 0x38;
  1323.         mt_cpufreq_pmic_volt[3] = 0x28;
  1324.         mt_cpufreq_pmic_volt[4] = 0x18;
  1325.     }
  1326.     else if((g_cpufreq_get_ptp_level >= 1) && (g_cpufreq_get_ptp_level <= 5))
  1327.     {
  1328.         mt65xx_reg_sync_writel(0x58, PMIC_WRAP_DVFS_WDATA0); // 1.25V VPROC
  1329.         mt65xx_reg_sync_writel(0x50, PMIC_WRAP_DVFS_WDATA1); // 1.20V VPROC
  1330.         mt65xx_reg_sync_writel(0x48, PMIC_WRAP_DVFS_WDATA2); // 1.15V VPROC
  1331.         mt65xx_reg_sync_writel(0x38, PMIC_WRAP_DVFS_WDATA3); // 1.05V VPROC
  1332.         mt65xx_reg_sync_writel(0x28, PMIC_WRAP_DVFS_WDATA4); // 0.95V VPROC
  1333.  
  1334.         /* For PTP-OD */
  1335.         mt_cpufreq_pmic_volt[0] = 0x58;
  1336.         mt_cpufreq_pmic_volt[1] = 0x50;
  1337.         mt_cpufreq_pmic_volt[2] = 0x48;
  1338.         mt_cpufreq_pmic_volt[3] = 0x38;
  1339.         mt_cpufreq_pmic_volt[4] = 0x28;
  1340.     }
  1341.     else
  1342.     {
  1343.         mt65xx_reg_sync_writel(0x50, PMIC_WRAP_DVFS_WDATA0); // 1.20V VPROC
  1344.         mt65xx_reg_sync_writel(0x48, PMIC_WRAP_DVFS_WDATA1); // 1.15V VPROC
  1345.         mt65xx_reg_sync_writel(0x38, PMIC_WRAP_DVFS_WDATA2); // 1.05V VPROC
  1346.         mt65xx_reg_sync_writel(0x28, PMIC_WRAP_DVFS_WDATA3); // 0.95V VPROC
  1347.         mt65xx_reg_sync_writel(0x18, PMIC_WRAP_DVFS_WDATA4); // 0.85V VPROC
  1348.  
  1349.         /* For PTP-OD */
  1350.         mt_cpufreq_pmic_volt[0] = 0x50;
  1351.         mt_cpufreq_pmic_volt[1] = 0x48;
  1352.         mt_cpufreq_pmic_volt[2] = 0x38;
  1353.         mt_cpufreq_pmic_volt[3] = 0x28;
  1354.         mt_cpufreq_pmic_volt[4] = 0x18;
  1355.     }
  1356.    
  1357.     mt65xx_reg_sync_writel(0x38, PMIC_WRAP_DVFS_WDATA5); // 1.05V VCORE
  1358.     mt65xx_reg_sync_writel(0x28, PMIC_WRAP_DVFS_WDATA6); // 0.95V VCORE
  1359.     mt65xx_reg_sync_writel(0x18, PMIC_WRAP_DVFS_WDATA7); // 0.85V VCORE
  1360.    
  1361.     xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "mt_cpufreq return default DVS by ptpod\n");
  1362. }
  1363. EXPORT_SYMBOL(mt_cpufreq_return_default_DVS_by_ptpod);
  1364.  
  1365. /************************************************
  1366. * DVFS enable API for PTPOD
  1367. *************************************************/
  1368. void mt_cpufreq_enable_by_ptpod(void)
  1369. {
  1370.     mt_cpufreq_ptpod_disable = false;
  1371.     xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "mt_cpufreq enabled by ptpod\n");
  1372. }
  1373. EXPORT_SYMBOL(mt_cpufreq_enable_by_ptpod);
  1374.  
  1375. /************************************************
  1376. * DVFS disable API for PTPOD
  1377. *************************************************/
  1378. unsigned int mt_cpufreq_disable_by_ptpod(void)
  1379. {
  1380.     struct cpufreq_policy *policy;
  1381.  
  1382.     mt_cpufreq_ptpod_disable = true;
  1383.  
  1384.     policy = cpufreq_cpu_get(0);
  1385.  
  1386.     if (!policy)
  1387.         goto no_policy;
  1388.  
  1389.     cpufreq_driver_target(policy, DVFS_F2, CPUFREQ_RELATION_L);
  1390.  
  1391.     xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "mt_cpufreq disabled by ptpod, limited freq. at %d\n", DVFS_F2);
  1392.  
  1393.     cpufreq_cpu_put(policy);
  1394.  
  1395. no_policy:
  1396.     return g_cur_freq;
  1397. }
  1398. EXPORT_SYMBOL(mt_cpufreq_disable_by_ptpod);
  1399.  
  1400. /************************************************
  1401. * frequency adjust interface for thermal protect
  1402. *************************************************/
  1403. /******************************************************
  1404. * parameter: target power
  1405. *******************************************************/
  1406. void mt_cpufreq_thermal_protect(unsigned int limited_power)
  1407. {
  1408.     int i = 0, ncpu = 0, found = 0;
  1409.  
  1410.     struct cpufreq_policy *policy;
  1411.  
  1412.     policy = cpufreq_cpu_get(0);
  1413.  
  1414.     if (!policy)
  1415.         goto no_policy;
  1416.  
  1417.     ncpu = num_possible_cpus();
  1418.  
  1419.     if (limited_power == 0)
  1420.     {
  1421.         g_limited_max_ncpu = num_possible_cpus();
  1422.         g_limited_max_freq = g_max_freq_by_ptp;
  1423.  
  1424.         cpufreq_driver_target(policy, g_limited_max_freq, CPUFREQ_RELATION_L);
  1425.         hp_limited_cpu_num(g_limited_max_ncpu);
  1426.  
  1427.         xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "thermal limit g_limited_max_freq = %d, g_limited_max_ncpu = %d\n", g_limited_max_freq, g_limited_max_ncpu);
  1428.     }
  1429.     else
  1430.     {
  1431.         while (ncpu)
  1432.         {
  1433.             for (i = 0; i < (mt_cpu_freqs_num * 4); i++)
  1434.             {
  1435.                 if (mt_cpu_power[i].cpufreq_ncpu == ncpu)
  1436.                 {
  1437.                     if (mt_cpu_power[i].cpufreq_power <= limited_power)
  1438.                     {
  1439.                         g_limited_max_ncpu = mt_cpu_power[i].cpufreq_ncpu;
  1440.                         g_limited_max_freq = mt_cpu_power[i].cpufreq_khz;
  1441.  
  1442.                         found = 1;
  1443.                         break;
  1444.                     }
  1445.                 }
  1446.             }
  1447.  
  1448.             if (found)
  1449.                 break;
  1450.  
  1451.             ncpu--;
  1452.         }
  1453.  
  1454.         if (!found)
  1455.         {
  1456.             xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "thermal limit fail, not found suitable DVFS OPP\n");
  1457.         }
  1458.         else
  1459.         {
  1460.             xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "thermal limit g_limited_max_freq = %d, g_limited_max_ncpu = %d\n", g_limited_max_freq, g_limited_max_ncpu);
  1461.  
  1462.             cpufreq_driver_target(policy, g_limited_max_freq, CPUFREQ_RELATION_L);
  1463.  
  1464.             hp_limited_cpu_num(g_limited_max_ncpu);
  1465.  
  1466.             if (num_online_cpus() > g_limited_max_ncpu)
  1467.             {
  1468.                 for (i = num_online_cpus(); i > g_limited_max_ncpu; i--)
  1469.                 {
  1470.                     xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "turn off CPU%d due to thermal protection\n", (i - 1));
  1471.                     cpu_down((i - 1));
  1472.                 }
  1473.             }
  1474.         }
  1475.     }
  1476.  
  1477.     cpufreq_cpu_put(policy);
  1478.  
  1479. no_policy:
  1480.     return;
  1481. }
  1482. EXPORT_SYMBOL(mt_cpufreq_thermal_protect);
  1483.  
  1484. /***************************
  1485. * show current DVFS stauts
  1486. ****************************/
  1487. static int mt_cpufreq_state_read(char *buf, char **start, off_t off, int count, int *eof, void *data)
  1488. {
  1489.     int len = 0;
  1490.     char *p = buf;
  1491.  
  1492.     if (!mt_cpufreq_pause)
  1493.         p += sprintf(p, "DVFS enabled\n");
  1494.     else
  1495.         p += sprintf(p, "DVFS disabled\n");
  1496.  
  1497.     len = p - buf;
  1498.     return len;
  1499. }
  1500.  
  1501. /************************************
  1502. * set DVFS stauts by sysfs interface
  1503. *************************************/
  1504. static ssize_t mt_cpufreq_state_write(struct file *file, const char *buffer, unsigned long count, void *data)
  1505. {
  1506.     int enabled = 0;
  1507.  
  1508.     if (sscanf(buffer, "%d", &enabled) == 1)
  1509.     {
  1510.         if (enabled == 1)
  1511.         {
  1512.             mt_cpufreq_state_set(1);
  1513.         }
  1514.         else if (enabled == 0)
  1515.         {
  1516.             mt_cpufreq_state_set(0);
  1517.         }
  1518.         else
  1519.         {
  1520.             xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "bad argument!! argument should be \"1\" or \"0\"\n");
  1521.         }
  1522.     }
  1523.     else
  1524.     {
  1525.         xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "bad argument!! argument should be \"1\" or \"0\"\n");
  1526.     }
  1527.  
  1528.     return count;
  1529. }
  1530.  
  1531. /****************************
  1532. * show current limited freq
  1533. *****************************/
  1534. static int mt_cpufreq_limited_power_read(char *buf, char **start, off_t off, int count, int *eof, void *data)
  1535. {
  1536.     int len = 0;
  1537.     char *p = buf;
  1538.  
  1539.     p += sprintf(p, "g_limited_max_freq = %d, g_limited_max_ncpu = %d\n", g_limited_max_freq, g_limited_max_ncpu);
  1540.  
  1541.     len = p - buf;
  1542.     return len;
  1543. }
  1544.  
  1545. /**********************************
  1546. * limited power for thermal protect
  1547. ***********************************/
  1548. static ssize_t mt_cpufreq_limited_power_write(struct file *file, const char *buffer, unsigned long count, void *data)
  1549. {
  1550.     unsigned int power = 0;
  1551.  
  1552.     if (sscanf(buffer, "%u", &power) == 1)
  1553.     {
  1554.         mt_cpufreq_thermal_protect(power);
  1555.         return count;
  1556.     }
  1557.     else
  1558.     {
  1559.         xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "bad argument!! please provide the maximum limited power\n");
  1560.     }
  1561.  
  1562.     return -EINVAL;
  1563. }
  1564.  
  1565. /***************************
  1566. * show current debug status
  1567. ****************************/
  1568. static int mt_cpufreq_debug_read(char *buf, char **start, off_t off, int count, int *eof, void *data)
  1569. {
  1570.     int len = 0;
  1571.     char *p = buf;
  1572.  
  1573.     if (mt_cpufreq_debug)
  1574.         p += sprintf(p, "cpufreq debug enabled\n");
  1575.     else
  1576.         p += sprintf(p, "cpufreq debug disabled\n");
  1577.  
  1578.     len = p - buf;
  1579.     return len;
  1580. }
  1581.  
  1582. /***********************
  1583. * enable debug message
  1584. ************************/
  1585. static ssize_t mt_cpufreq_debug_write(struct file *file, const char *buffer, unsigned long count, void *data)
  1586. {
  1587.     int debug = 0;
  1588.  
  1589.     if (sscanf(buffer, "%d", &debug) == 1)
  1590.     {
  1591.         if (debug == 0)
  1592.         {
  1593.             mt_cpufreq_debug = 0;
  1594.             return count;
  1595.         }
  1596.         else if (debug == 1)
  1597.         {
  1598.             mt_cpufreq_debug = 1;
  1599.             return count;
  1600.         }
  1601.         else
  1602.         {
  1603.             xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "bad argument!! should be 0 or 1 [0: disable, 1: enable]\n");
  1604.         }
  1605.     }
  1606.     else
  1607.     {
  1608.         xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "bad argument!! should be 0 or 1 [0: disable, 1: enable]\n");
  1609.     }
  1610.  
  1611.     return -EINVAL;
  1612. }
  1613.  
  1614. /***************************
  1615. * show cpufreq power info
  1616. ****************************/
  1617. static int mt_cpufreq_power_dump_read(char *buf, char **start, off_t off, int count, int *eof, void *data)
  1618. {
  1619.     int i = 0, len = 0;
  1620.     char *p = buf;
  1621.  
  1622.     for (i = 0; i < (mt_cpu_freqs_num * 4); i++)
  1623.     {
  1624.         xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "mt_cpu_power[%d].cpufreq_khz = %d\n", i, mt_cpu_power[i].cpufreq_khz);
  1625.         xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "mt_cpu_power[%d].cpufreq_ncpu = %d\n", i, mt_cpu_power[i].cpufreq_ncpu);
  1626.         xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "mt_cpu_power[%d].cpufreq_power = %d\n", i, mt_cpu_power[i].cpufreq_power);
  1627.     }
  1628.  
  1629.     p += sprintf(p, "done\n");
  1630.  
  1631.     len = p - buf;
  1632.     return len;
  1633. }
  1634.  
  1635. /*******************************************
  1636. * cpufrqe platform driver callback function
  1637. ********************************************/
  1638. static int mt_cpufreq_pdrv_probe(struct platform_device *pdev)
  1639. {
  1640.     #ifdef CONFIG_HAS_EARLYSUSPEND
  1641.     mt_cpufreq_early_suspend_handler.suspend = mt_cpufreq_early_suspend;
  1642.     mt_cpufreq_early_suspend_handler.resume = mt_cpufreq_late_resume;
  1643.     register_early_suspend(&mt_cpufreq_early_suspend_handler);
  1644.     #endif
  1645.  
  1646.     /************************************************
  1647.     * Check PTP level to define default max freq
  1648.     *************************************************/
  1649.     g_cpufreq_get_ptp_level = PTP_get_ptp_level();
  1650.    
  1651.     if(g_cpufreq_get_ptp_level == 0)
  1652.         g_max_freq_by_ptp = DVFS_F1;
  1653.     else if(g_cpufreq_get_ptp_level == 1)
  1654.         g_max_freq_by_ptp = DVFS_F0_4;
  1655.     else if(g_cpufreq_get_ptp_level == 2)
  1656.         g_max_freq_by_ptp = DVFS_F0_3;
  1657.     else if(g_cpufreq_get_ptp_level == 3)
  1658.         g_max_freq_by_ptp = DVFS_F0_2;
  1659.     else if(g_cpufreq_get_ptp_level == 4)
  1660.         g_max_freq_by_ptp = DVFS_F0_1;
  1661.     else if(g_cpufreq_get_ptp_level == 5)
  1662.         g_max_freq_by_ptp = DVFS_F0_0;
  1663.     else
  1664.         g_max_freq_by_ptp = DVFS_F1;
  1665.    
  1666.     /************************************************
  1667.     * voltage scaling need to wait PMIC driver ready
  1668.     *************************************************/
  1669.     mt_cpufreq_ready = true;
  1670.  
  1671.     g_cur_freq = DVFS_F2;
  1672.     g_cur_cpufreq_volt = DVFS_V2;
  1673.     g_limited_max_freq = g_max_freq_by_ptp;
  1674.     g_limited_min_freq = DVFS_F4;
  1675.  
  1676.     /* Check if max freq over 1.2GHz, When early suspend, limit max freq. */
  1677.     if(g_max_freq_by_ptp > DVFS_F1)
  1678.     {
  1679.         mt_cpufreq_max_freq_overdrive = true;
  1680.     }
  1681.    
  1682.     xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "mediatek cpufreq initialized\n");
  1683.  
  1684.     if(g_cpufreq_get_ptp_level == 0)
  1685.         spm_dvfs_ctrl_volt(1); // default set to 1.15V
  1686.     else if((g_cpufreq_get_ptp_level >= 1) && (g_cpufreq_get_ptp_level <= 5))
  1687.         spm_dvfs_ctrl_volt(2); // default set to 1.15V
  1688.     else
  1689.         spm_dvfs_ctrl_volt(1); // default set to 1.15V
  1690.        
  1691.     mt65xx_reg_sync_writel(0x021A, PMIC_WRAP_DVFS_ADR0);
  1692.     mt65xx_reg_sync_writel(0x021A, PMIC_WRAP_DVFS_ADR1);
  1693.     mt65xx_reg_sync_writel(0x021A, PMIC_WRAP_DVFS_ADR2);
  1694.     mt65xx_reg_sync_writel(0x021A, PMIC_WRAP_DVFS_ADR3);
  1695.     mt65xx_reg_sync_writel(0x021A, PMIC_WRAP_DVFS_ADR4);
  1696.     mt65xx_reg_sync_writel(0x026C, PMIC_WRAP_DVFS_ADR5);
  1697.     mt65xx_reg_sync_writel(0x026C, PMIC_WRAP_DVFS_ADR6);
  1698.     mt65xx_reg_sync_writel(0x026C, PMIC_WRAP_DVFS_ADR7);
  1699.  
  1700.     if(g_cpufreq_get_ptp_level == 0)
  1701.     {
  1702.         mt65xx_reg_sync_writel(0x50, PMIC_WRAP_DVFS_WDATA0); // 1.20V VPROC
  1703.         mt65xx_reg_sync_writel(0x48, PMIC_WRAP_DVFS_WDATA1); // 1.15V VPROC
  1704.         mt65xx_reg_sync_writel(0x38, PMIC_WRAP_DVFS_WDATA2); // 1.05V VPROC
  1705.         mt65xx_reg_sync_writel(0x28, PMIC_WRAP_DVFS_WDATA3); // 0.95V VPROC
  1706.         mt65xx_reg_sync_writel(0x18, PMIC_WRAP_DVFS_WDATA4); // 0.85V VPROC
  1707.  
  1708.         /* For PTP-OD */
  1709.         mt_cpufreq_pmic_volt[0] = 0x50;
  1710.         mt_cpufreq_pmic_volt[1] = 0x48;
  1711.         mt_cpufreq_pmic_volt[2] = 0x38;
  1712.         mt_cpufreq_pmic_volt[3] = 0x28;
  1713.         mt_cpufreq_pmic_volt[4] = 0x18;
  1714.     }
  1715.     else if((g_cpufreq_get_ptp_level >= 1) && (g_cpufreq_get_ptp_level <= 5))
  1716.     {
  1717.         mt65xx_reg_sync_writel(0x58, PMIC_WRAP_DVFS_WDATA0); // 1.25V VPROC
  1718.         mt65xx_reg_sync_writel(0x50, PMIC_WRAP_DVFS_WDATA1); // 1.20V VPROC
  1719.         mt65xx_reg_sync_writel(0x48, PMIC_WRAP_DVFS_WDATA2); // 1.15V VPROC
  1720.         mt65xx_reg_sync_writel(0x38, PMIC_WRAP_DVFS_WDATA3); // 1.05V VPROC
  1721.         mt65xx_reg_sync_writel(0x28, PMIC_WRAP_DVFS_WDATA4); // 0.95V VPROC
  1722.  
  1723.         /* For PTP-OD */
  1724.         mt_cpufreq_pmic_volt[0] = 0x58;
  1725.         mt_cpufreq_pmic_volt[1] = 0x50;
  1726.         mt_cpufreq_pmic_volt[2] = 0x48;
  1727.         mt_cpufreq_pmic_volt[3] = 0x38;
  1728.         mt_cpufreq_pmic_volt[4] = 0x28;
  1729.     }
  1730.     else
  1731.     {
  1732.         mt65xx_reg_sync_writel(0x50, PMIC_WRAP_DVFS_WDATA0); // 1.20V VPROC
  1733.         mt65xx_reg_sync_writel(0x48, PMIC_WRAP_DVFS_WDATA1); // 1.15V VPROC
  1734.         mt65xx_reg_sync_writel(0x38, PMIC_WRAP_DVFS_WDATA2); // 1.05V VPROC
  1735.         mt65xx_reg_sync_writel(0x28, PMIC_WRAP_DVFS_WDATA3); // 0.95V VPROC
  1736.         mt65xx_reg_sync_writel(0x18, PMIC_WRAP_DVFS_WDATA4); // 0.85V VPROC
  1737.  
  1738.         /* For PTP-OD */
  1739.         mt_cpufreq_pmic_volt[0] = 0x50;
  1740.         mt_cpufreq_pmic_volt[1] = 0x48;
  1741.         mt_cpufreq_pmic_volt[2] = 0x38;
  1742.         mt_cpufreq_pmic_volt[3] = 0x28;
  1743.         mt_cpufreq_pmic_volt[4] = 0x18;
  1744.     }
  1745.    
  1746.     mt65xx_reg_sync_writel(0x38, PMIC_WRAP_DVFS_WDATA5); // 1.05V VCORE
  1747.     mt65xx_reg_sync_writel(0x28, PMIC_WRAP_DVFS_WDATA6); // 0.95V VCORE
  1748.     mt65xx_reg_sync_writel(0x18, PMIC_WRAP_DVFS_WDATA7); // 0.85V VCORE
  1749.  
  1750.     /* MT6320 DVS down software solution. */
  1751.     #ifdef CPU_DVS_DOWN_SW_SOL
  1752.     pmic_dvs_init_setting();
  1753.     #endif
  1754.    
  1755.     return cpufreq_register_driver(&mt_cpufreq_driver);
  1756. }
  1757.  
  1758. static int mt_cpufreq_suspend(struct device *device)
  1759. {
  1760.     xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "mt_cpufreq_suspend\n");
  1761.     #ifdef CPU_DVS_DOWN_SW_SOL
  1762.     pmic_dvs_into_suspend_set_before_volt_change();
  1763.     #endif
  1764.    
  1765.     return 0;
  1766. }
  1767.  
  1768. static int mt_cpufreq_resume(struct device *device)
  1769. {
  1770.     xlog_printk(ANDROID_LOG_INFO, "Power/DVFS", "mt_cpufreq_resume\n");
  1771.  
  1772.     return 0;
  1773. }
  1774.  
  1775. /***************************************
  1776. * this function should never be called
  1777. ****************************************/
  1778. static int mt_cpufreq_pdrv_remove(struct platform_device *pdev)
  1779. {
  1780.     return 0;
  1781. }
  1782.  
  1783. struct dev_pm_ops mt_cpufreq_pdrv_pm_ops = {
  1784.     .suspend = mt_cpufreq_suspend,
  1785.     .resume = mt_cpufreq_resume,
  1786.     .freeze = mt_cpufreq_suspend,
  1787.     .thaw = mt_cpufreq_resume,
  1788.     .poweroff = NULL,
  1789.     .restore = mt_cpufreq_resume,
  1790.     .restore_noirq = NULL,
  1791. };
  1792.  
  1793. static struct platform_driver mt_cpufreq_pdrv = {
  1794.     .probe      = mt_cpufreq_pdrv_probe,
  1795.     .remove     = mt_cpufreq_pdrv_remove,
  1796.     .driver     = {
  1797. #ifdef CONFIG_PM
  1798.         .pm     = &mt_cpufreq_pdrv_pm_ops,
  1799. #endif
  1800.         .name   = "mt-cpufreq",
  1801.         .owner  = THIS_MODULE,
  1802.     },
  1803. };
  1804.  
  1805. /***********************************************************
  1806. * cpufreq initialization to register cpufreq platform driver
  1807. ************************************************************/
  1808. static int __init mt_cpufreq_pdrv_init(void)
  1809. {
  1810.     int ret = 0;
  1811.  
  1812.     struct proc_dir_entry *mt_entry = NULL;
  1813.     struct proc_dir_entry *mt_cpufreq_dir = NULL;
  1814.  
  1815.     mt_cpufreq_dir = proc_mkdir("cpufreq", NULL);
  1816.     if (!mt_cpufreq_dir)
  1817.     {
  1818.         pr_err("[%s]: mkdir /proc/cpufreq failed\n", __FUNCTION__);
  1819.     }
  1820.     else
  1821.     {
  1822.         mt_entry = create_proc_entry("cpufreq_debug", S_IRUGO | S_IWUSR | S_IWGRP, mt_cpufreq_dir);
  1823.         if (mt_entry)
  1824.         {
  1825.             mt_entry->read_proc = mt_cpufreq_debug_read;
  1826.             mt_entry->write_proc = mt_cpufreq_debug_write;
  1827.         }
  1828.  
  1829.         mt_entry = create_proc_entry("cpufreq_limited_power", S_IRUGO | S_IWUSR | S_IWGRP, mt_cpufreq_dir);
  1830.         if (mt_entry)
  1831.         {
  1832.             mt_entry->read_proc = mt_cpufreq_limited_power_read;
  1833.             mt_entry->write_proc = mt_cpufreq_limited_power_write;
  1834.         }
  1835.  
  1836.         mt_entry = create_proc_entry("cpufreq_state", S_IRUGO | S_IWUSR | S_IWGRP, mt_cpufreq_dir);
  1837.         if (mt_entry)
  1838.         {
  1839.             mt_entry->read_proc = mt_cpufreq_state_read;
  1840.             mt_entry->write_proc = mt_cpufreq_state_write;
  1841.         }
  1842.  
  1843.         mt_entry = create_proc_entry("cpufreq_power_dump", S_IRUGO | S_IWUSR | S_IWGRP, mt_cpufreq_dir);
  1844.         if (mt_entry)
  1845.         {
  1846.             mt_entry->read_proc = mt_cpufreq_power_dump_read;
  1847.         }
  1848.     }
  1849.  
  1850.     ret = platform_driver_register(&mt_cpufreq_pdrv);
  1851.     if (ret)
  1852.     {
  1853.         xlog_printk(ANDROID_LOG_ERROR, "Power/DVFS", "failed to register cpufreq driver\n");
  1854.         return ret;
  1855.     }
  1856.     else
  1857.     {
  1858.         xlog_printk(ANDROID_LOG_ERROR, "Power/DVFS", "cpufreq driver registration done\n");
  1859.         xlog_printk(ANDROID_LOG_ERROR, "Power/DVFS", "g_cpufreq_get_ptp_level = %d\n", g_cpufreq_get_ptp_level);
  1860.         return 0;
  1861.     }
  1862. }
  1863.  
  1864. static void __exit mt_cpufreq_pdrv_exit(void)
  1865. {
  1866.     cpufreq_unregister_driver(&mt_cpufreq_driver);
  1867. }
  1868.  
  1869. module_init(mt_cpufreq_pdrv_init);
  1870. module_exit(mt_cpufreq_pdrv_exit);
  1871.  
  1872. MODULE_DESCRIPTION("MediaTek CPU Frequency Scaling driver");
  1873. MODULE_LICENSE("GPL");
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