RedBoot> load /kernel
Using default protocol (TFTP)
Entry point: 0x80050100, address range: 0x80050000-0x804a2378
RedBoot> exec
Now booting linux kernel:
 Base address 0x80050000 Entry 0x80050100
 Cmdline : console=ttyS0,115200 init=/init
platform frequency: 680000000
arguments:
  a0 = 00000002
  a1 = 80050028
  a2 = 80050000
  a3 = 0000001b
Cmd line:  console=ttyS0,115200 init=/init
Environment:
  memsize = 0x04000000
  modetty0 = 0,n,8,1,hw
  ethaddr = 00.15.6d.c1.bc.a9
  board = Ubiquiti AR71xx-based board
Cache info:
  picache_stride    = 4096
  picache_loopcount = 16
  pdcache_stride    = 4096
  pdcache_loopcount = 8
cpu0: MIPS Technologies processor v116.147
  MMU: Standard TLB, 16 entries
  L1 i-cache: 4 ways of 512 sets, 32 bytes per line
  L1 d-cache: 4 ways of 256 sets, 32 bytes per line
  Config1=0x9ee3519e<PerfCount,WatchRegs,MIPS16,EJTAG>
  Config3=0x20
KDB: debugger backends: ddb
KDB: current backend: ddb
Copyright (c) 1992-2010 The FreeBSD Project.
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
        The Regents of the University of California. All rights reserved.
FreeBSD is a registered trademark of The FreeBSD Foundation.
FreeBSD 9.0-CURRENT #2 r209378M: Sat Jun 26 09:03:21 BRT 2010
    porks@BARAD-DUR.BUTECO:/mnt/ad2s1d/data/mips/obj/mips/mnt/ad1s1d/data/src/sys/AR71XX mips
Trap cause = 2 (TLB miss (load or instr. fetch) - kernel mode)
Trap cause = 2 (TLB miss (load or instr. fetch) - kernel mode)
panic: trap
Uptime: 1s