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  1. /*
  2.  * Copyright 2014 John Weber, Avnet Electronics Marketing
  3.  * Copyright 2013 Boundary Devices
  4.  * Copyright 2012 Freescale Semiconductor, Inc.
  5.  * Copyright 2011 Linaro Ltd.
  6.  *
  7.  * The code contained herein is licensed under the GNU General Public
  8.  * License. You may obtain a copy of the GNU General Public License
  9.  * Version 2 or later at the following locations:
  10.  *
  11.  * http://www.opensource.org/licenses/gpl-license.html
  12.  * http://www.gnu.org/copyleft/gpl.html
  13.  */
  14.  
  15. / {
  16.     aliases {
  17.         mxcfb0 = &mxcfb1;
  18.         mxcfb1 = &mxcfb2;
  19.         mxcfb2 = &mxcfb3;
  20.         mxcfb3 = &mxcfb4;
  21.     };
  22.  
  23.     memory {
  24.         reg = <0x10000000 0x40000000>;
  25.     };
  26.  
  27.     regulators {
  28.         compatible = "simple-bus";
  29.  
  30.         reg_1p8v: 1p8v {
  31.             compatible = "regulator-fixed";
  32.             regulator-name = "1P8V";
  33.             regulator-min-microvolt = <1800000>;
  34.             regulator-max-microvolt = <1800000>;
  35.             regulator-always-on;
  36.         };
  37.  
  38.         reg_2p5v: 2p5v {
  39.             compatible = "regulator-fixed";
  40.             regulator-name = "2P5V";
  41.             regulator-min-microvolt = <2500000>;
  42.             regulator-max-microvolt = <2500000>;
  43.             regulator-always-on;
  44.         };
  45.  
  46.         reg_3p3v: 3p3v {
  47.             compatible = "regulator-fixed";
  48.             regulator-name = "3P3V";
  49.             regulator-min-microvolt = <3300000>;
  50.             regulator-max-microvolt = <3300000>;
  51.             regulator-always-on;
  52.         };
  53.  
  54.         reg_usb_otg_vbus: usb_otg_vbus {
  55.             compatible = "regulator-fixed";
  56.             regulator-name = "usb_otg_vbus";
  57.             regulator-min-microvolt = <5000000>;
  58.             regulator-max-microvolt = <5000000>;
  59.             gpio = <&gpio1 1 GPIO_ACTIVE_LOW>;
  60.             enable-active-high;
  61.         };
  62.     };
  63.  
  64.     sound {
  65.         compatible = "fsl,imx6-wandboard-sgtl5000",
  66.                              "fsl,imx-audio-sgtl5000";
  67.         model = "imx6-wandboard-sgtl5000";
  68.         ssi-controller = <&ssi1>;
  69.         audio-codec = <&codec>;
  70.         audio-routing =
  71.             "MIC_IN", "Mic Jack",
  72.             "Mic Jack", "Mic Bias",
  73.             "Headphone Jack", "HP_OUT";
  74.         mux-int-port = <1>;
  75.         mux-ext-port = <3>;
  76.     };
  77.  
  78.         sound-spdif {
  79.                 compatible = "fsl,imx-audio-spdif";
  80.                 model = "imx-spdif";
  81.                 spdif-controller = <&spdif>;
  82.                 spdif-out;
  83.         };
  84.  
  85.     sound-hdmi {
  86.         compatible = "fsl,imx6q-audio-hdmi",
  87.                  "fsl,imx-audio-hdmi";
  88.         model = "imx-audio-hdmi";
  89.         hdmi-controller = <&hdmi_audio>;
  90.     };
  91.  
  92.         rfkill {
  93.                 compatible = "wand,imx6qdl-wandboard-rfkill";
  94.                 pinctrl-names = "default";
  95.                 pinctrl-0 = <>;
  96.  
  97.                 bluetooth-on = <&gpio3 13 0>;
  98.                 bluetooth-wake = <&gpio3 14 0>;
  99.                 bluetooth-host-wake = <&gpio3 15 0>;
  100.  
  101.                 wifi-ref-on = <&gpio2 29 0>;
  102.                 wifi-rst-n = <&gpio5 2 0>;
  103.                 wifi-reg-on = <&gpio1 26 0>;
  104.                 wifi-host-wake = <&gpio1 29 0>;
  105.                 wifi-wake = <&gpio1 30 0>;
  106.         };
  107.  
  108.     mxcfb1: fb@0 {
  109.         compatible = "fsl,mxc_sdc_fb";
  110.         disp_dev = "ldb";
  111.         interface_pix_fmt = "RGB666";
  112.         mode_str ="LDB-XGA";
  113.         default_bpp = <24>;
  114.         int_clk = <0>;
  115.         late_init = <0>;
  116.         status = "disabled";
  117.     };
  118.  
  119.         mxcfb2: fb@1 {
  120.                 compatible = "fsl,mxc_sdc_fb";
  121.                 disp_dev = "ldb";
  122.                 interface_pix_fmt = "RGB666";
  123.                 mode_str ="LDB-XGA";
  124.                 default_bpp = <16>;
  125.                 int_clk = <0>;
  126.                 late_init = <0>;
  127.                 status = "disabled";
  128.         };
  129.  
  130.     mxcfb3: fb@2 {
  131.         compatible = "fsl,mxc_sdc_fb";
  132.         disp_dev = "lcd";
  133.         interface_pix_fmt = "RGB565";
  134.         mode_str ="CLAA-WVGA";
  135.         default_bpp = <16>;
  136.         int_clk = <0>;
  137.         late_init = <0>;
  138.         status = "disabled";
  139.     };
  140.  
  141.     mxcfb4: fb@3 {
  142.         compatible = "fsl,mxc_sdc_fb";
  143.         disp_dev = "ldb";
  144.         interface_pix_fmt = "RGB666";
  145.         mode_str ="LDB-XGA";
  146.         default_bpp = <16>;
  147.         int_clk = <0>;
  148.         late_init = <0>;
  149.         status = "disabled";
  150.     };
  151.  
  152. #if 0
  153.     lcd@0 {
  154.         compatible = "fsl,lcd";
  155.         ipu_id = <0>;
  156.         disp_id = <0>;
  157.         default_ifmt = "RGB565";
  158.         pinctrl-names = "default";
  159.         pinctrl-0 = <&pinctrl_ipu1_4>;
  160. #if 0
  161.         status = "okay";
  162. #endif
  163.     };
  164.  
  165.     backlight_lcd {
  166.         compatible = "pwm-backlight";
  167.         pwms = <&pwm1 0 5000000>;
  168.         brightness-levels = <0 4 8 16 32 64 128 255>;
  169.         default-brightness-level = <7>;
  170.     };
  171.  
  172.     backlight_lvds {
  173.         compatible = "pwm-backlight";
  174.         pwms = <&pwm4 0 5000000>;
  175.         brightness-levels = <0 4 8 16 32 64 128 255>;
  176.         default-brightness-level = <7>;
  177.     };
  178. #endif
  179.     v4l2_cap_0 {
  180.         compatible = "fsl,imx6q-v4l2-capture";
  181.         ipu_id = <0>;
  182.         csi_id = <0>;
  183.         mclk_source = <0>;
  184.         status = "okay";
  185.     };
  186.  
  187.     v4l2_out {
  188.         compatible = "fsl,mxc_v4l2_output";
  189.         status = "okay";
  190.     };
  191.  
  192. };
  193.  
  194.  
  195. &audmux {
  196.     pinctrl-names = "default";
  197.     pinctrl-0 = <&pinctrl_audmux_2>;
  198.     status = "okay";
  199. };
  200.  
  201.  
  202. &fec {
  203.     pinctrl-names = "default";
  204.     pinctrl-0 = <&pinctrl_enet_3>;
  205.     phy-mode = "rgmii";
  206.     status = "okay";
  207. };
  208.  
  209. &hdmi_audio {
  210.     status = "okay";
  211. };
  212.  
  213. &hdmi_core {
  214.     ipu_id = <0>;
  215.     disp_id = <0>;
  216.     status = "okay";
  217. };
  218.  
  219. &hdmi_video {
  220.     fsl,phy_reg_vlev = <0x0294>;
  221.     fsl,phy_reg_cksymtx = <0x800d>;
  222.     status = "okay";
  223. };
  224.  
  225. &i2c1 {
  226.     clock-frequency = <100000>;
  227.     pinctrl-names = "default";
  228.     pinctrl-0 = <&pinctrl_i2c1_1>;
  229.     status = "okay";
  230.  
  231.     hdmi: edid@50 {
  232.         compatible = "fsl,imx6-hdmi-i2c";
  233.         reg = <0x50>;
  234.     };
  235.  
  236. };
  237.  
  238. &i2c2 {
  239.     clock-frequency = <100000>;
  240.     pinctrl-names = "default";
  241.     pinctrl-0 = <&pinctrl_i2c2_2>;
  242.     status = "okay";
  243.  
  244.     ov5640_mipi: ov5640_mipi@3c {
  245.         compatible = "ovti,ov5640_mipi";
  246.         reg = <0x3c>;
  247.         clocks = <&clks 200>;
  248.         clock-names = "csi_mclk";
  249.         DOVDD-supply = <&reg_1p8v>;
  250.         AVDD-supply = <&reg_2p5v>;
  251.         DVDD-supply = <&reg_1p8v>;
  252.         pwn-gpios = <&gpio1 6 1>;
  253.         rst-gpios = <&gpio4 14 0>;
  254.         ipu_id = <0>;
  255.         csi_id = <0>;
  256.         mclk = <24000000>;
  257.         mclk_source = <0>;
  258.     };
  259.  
  260.     codec: sgtl5000@0a {
  261.         compatible = "fsl,sgtl5000";
  262.         reg = <0x0a>;
  263.         clocks = <&clks 201>;
  264.         VDDA-supply = <&reg_2p5v>;
  265.         VDDIO-supply = <&reg_3p3v>;
  266.     };
  267. };
  268.  
  269. &i2c3 {
  270.         clock-frequency = <100000>;
  271.         pinctrl-names = "default";
  272.         pinctrl-0 = <&pinctrl_i2c3_3>;
  273.         status = "okay";
  274. };
  275.  
  276. /*
  277. For reference here, the PAD_CTL bitfield definition from
  278. Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
  279.  
  280. CONFIG bits definition:
  281. PAD_CTL_HYS                     (1 << 16)
  282. PAD_CTL_PUS_100K_DOWN           (0 << 14)
  283. PAD_CTL_PUS_47K_UP              (1 << 14)
  284. PAD_CTL_PUS_100K_UP             (2 << 14)
  285. PAD_CTL_PUS_22K_UP              (3 << 14)
  286. PAD_CTL_PUE                     (1 << 13)
  287. PAD_CTL_PKE                     (1 << 12)
  288. PAD_CTL_ODE                     (1 << 11)
  289. PAD_CTL_SPEED_LOW               (1 << 6)
  290. PAD_CTL_SPEED_MED               (2 << 6)
  291. PAD_CTL_SPEED_HIGH              (3 << 6)
  292. PAD_CTL_DSE_DISABLE             (0 << 3)
  293. PAD_CTL_DSE_240ohm              (1 << 3)
  294. PAD_CTL_DSE_120ohm              (2 << 3)
  295. PAD_CTL_DSE_80ohm               (3 << 3)
  296. PAD_CTL_DSE_60ohm               (4 << 3)
  297. PAD_CTL_DSE_48ohm               (5 << 3)
  298. PAD_CTL_DSE_40ohm               (6 << 3)
  299. PAD_CTL_DSE_34ohm               (7 << 3)
  300. PAD_CTL_SRE_FAST                (1 << 0)
  301. PAD_CTL_SRE_SLOW                (0 << 0)
  302.  
  303. Example, the Control Pad Setting
  304.  
  305.     0x0f0b0
  306.  
  307. corresponds to:
  308.  
  309.    0b1111000010110000
  310.  
  311. which is:
  312.  
  313.    PAD_CTL_PUS_22K_UP | PAD_CTL_PUE | PAD_CTL_PKE |
  314.    PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm
  315.  
  316. For more information about this, refer to the IOMUXC section of the i.MX6
  317. reference manual.
  318.  
  319. */
  320.  
  321. &iomuxc {
  322.     pinctrl-names = "default";
  323.     pinctrl-0 = <&pinctrl_hog_1>;
  324.  
  325.     imx6qdl-wandboard {
  326.         pinctrl_hog_1: hoggrp-1 {
  327.             fsl,pins = <
  328.                 MX6QDL_PAD_GPIO_0__CCM_CLKO1         0x130b0
  329.                 MX6QDL_PAD_EIM_D22__GPIO3_IO22        0x80000000    /* USB Power Enable */
  330.                 MX6QDL_PAD_GPIO_2__GPIO1_IO02        0x80000000    /* USDHC1 CD */
  331.                 MX6QDL_PAD_EIM_DA9__GPIO3_IO09        0x80000000    /* uSDHC3 CD */
  332.                 MX6QDL_PAD_GPIO_0__CCM_CLKO1        0x000b0        /* SGTL5000 sys_mclk */
  333.                 MX6QDL_PAD_GPIO_6__GPIO1_IO06        0x0b0b0        /* ov5640 mipi powerdown */
  334.                 MX6QDL_PAD_KEY_COL4__GPIO4_IO14        0x000b0        /* ov5640 mipi reset */
  335.                 MX6QDL_PAD_GPIO_3__CCM_CLKO2        0x000b0        /* ov5640 mclk */
  336.                 MX6QDL_PAD_EIM_A25__GPIO5_IO02        0x0f0b0        /* WIFI_ON (reset, active low) */
  337.                 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26    0x000b0        /* WL_REG_ON (unused) */
  338.                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29    0x80000000    /* WL_HOST_WAKE, input */
  339.                 MX6QDL_PAD_EIM_EB1__GPIO2_IO29        0x0f0b0        /* EIM_EB1 (Wifi Power Enable) */
  340.                 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30    0x80000000    /* WL_WAKE (unused) */
  341.                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29       0x80000000
  342.                                 MX6QDL_PAD_EIM_DA13__GPIO3_IO13      0x80000000     /* BT_ON */
  343.                                 MX6QDL_PAD_EIM_DA14__GPIO3_IO14      0x80000000     /* BT_WAKE */
  344.                                 MX6QDL_PAD_EIM_DA15__GPIO3_IO15      0x80000000     /* BT_HOST_WAKE */
  345.             >;
  346.         };
  347.  
  348.             pinctrl_spdif_wand: spdifgrp {
  349.                     fsl,pins = <
  350.                 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT                 0x1b0b0
  351.             >;
  352.             };
  353.     };
  354.     gpio {
  355.         pinctrl_gpio: gpiogrp {
  356.             fsl,pins = <
  357.                                 MX6QDL_PAD_EIM_DA12__GPIO3_IO12   0x80000000 /* GPIO3_12 EDM pin 255 */
  358.                                 MX6QDL_PAD_EIM_DA11__GPIO3_IO11   0x80000000 /* GPIO3_11 EDM pin 256 */
  359.                                 MX6QDL_PAD_EIM_DA10__GPIO3_IO10   0x80000000 /* GPIO3_10 EDM pin 257 */
  360.                                 MX6QDL_PAD_EIM_D27__GPIO3_IO27    0x80000000 /* GPIO3_27 EDM pin 258 */
  361.                                 MX6QDL_PAD_EIM_D26__GPIO3_IO26    0x80000000 /* GPIO3_26 EDM pin 259 */
  362.                                 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31   0x80000000 /* GPIO6_31 EDM pin 260 */
  363.                                 MX6QDL_PAD_EIM_DA8__GPIO3_IO08    0x80000000 /* GPIO3_8  EDM pin 261 */
  364.                                 MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x80000000 /* GPIO1_24 EDM pin 262 */
  365.                                 MX6QDL_PAD_GPIO_19__GPIO4_IO05    0x80000000 /* GPIO4_5  EDM pin 263 */
  366.                                 MX6QDL_PAD_SD3_RST__GPIO7_IO08    0x80000000 /* GPIO7_8  EDM pin 264 */
  367.             >;
  368.         };
  369.     };
  370. };
  371.  
  372. &ldb {
  373.     ipu_id = <0>;
  374.     disp_id = <1>;
  375.     ext_ref = <1>;
  376.     mode = "sin0";
  377.     sec_ipu_id = <1>;
  378.     sec_disp_id = <1>;
  379.     status = "okay";
  380. };
  381.  
  382.  
  383. &mipi_csi {
  384.     ipu_id = <0>;
  385.     csi_id = <0>;
  386.     v_channel = <0>;
  387.     lanes = <2>;
  388.     status = "okay";
  389. };
  390.  
  391. &pcie {
  392.     status = "okay";
  393. };
  394.  
  395. #if 0
  396. &pwm1 {
  397.     pinctrl-names = "default";
  398.     pinctrl-0 = <&pinctrl_pwm1_1>;
  399.     status = "okay";
  400. };
  401.  
  402. &pwm3 {
  403.     pinctrl-names = "default";
  404.     pinctrl-0 = <&pinctrl_pwm3_2>;
  405.     status = "okay";
  406. };
  407.  
  408. &pwm4 {
  409.     pinctrl-names = "default";
  410.     pinctrl-0 = <&pinctrl_pwm4_2>;
  411.     status = "okay";
  412. };
  413. #endif
  414.  
  415. &spdif {
  416.         pinctrl-names = "default";
  417.         pinctrl-0 = <&pinctrl_spdif_wand>;
  418.         status = "okay";
  419. };
  420.  
  421. &ssi1 {
  422.     fsl,mode = "i2s-slave";
  423.     status = "okay";
  424. };
  425.  
  426. &uart1 {
  427.     pinctrl-names = "default";
  428.     pinctrl-0 = <&pinctrl_uart1_1>;
  429.     status = "okay";
  430. };
  431.  
  432. &uart3 {
  433.         pinctrl-names = "default";
  434.         pinctrl-0 = <&pinctrl_uart3_1>;
  435.         fsl,uart-has-rtscts;
  436.         status = "okay";
  437. };
  438.  
  439. &usbh1 {
  440.     status = "okay";
  441. };
  442.  
  443. &usbotg {
  444.     vbus-supply = <&reg_usb_otg_vbus>;
  445.     pinctrl-names = "default";
  446.     pinctrl-0 = <&pinctrl_usbotg_1>;
  447.     disable-over-current;
  448.     dr_mode = "peripheral";
  449.     status = "okay";
  450. };
  451.  
  452. &usdhc1 {  /* Baseboard microSD slot */
  453.     pinctrl-names = "default";
  454.     pinctrl-0 = <&pinctrl_usdhc1_1>;
  455.     bus-width = <4>;
  456.     vmmc-supply = <&reg_3p3v>;
  457.     cd-gpios = <&gpio1 2 0>;
  458.     status = "okay";
  459. };
  460.  
  461. &usdhc2 {  /* Broadcom Wifi/BT  */
  462.     pinctrl-names = "default";
  463.     pinctrl-0 = <&pinctrl_usdhc2_2>;
  464.     bus-width = <4>;
  465.     //non-removable;
  466.     vmmc-supply = <&reg_3p3v>;
  467.     keep-power-in-suspend;
  468.     status = "okay";
  469. };
  470.  
  471. &usdhc3 { /* Module microSD slot */
  472.     pinctrl-names = "default";
  473.     pinctrl-0 = <&pinctrl_usdhc3_2>;
  474.     vmmc-supply = <&reg_3p3v>;
  475.         cd-gpios = <&gpio3 9 0>;
  476.     status = "okay";
  477. };
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