ACTUAL CODE:
class _CommandChooser(Module):
	def __init__(self, requests):
		self.want_reads = Signal()
		self.want_writes = Signal()
		self.want_cmds = Signal()
		# NB: cas_n/ras_n/we_n are 1 when stb is inactive
		self.cmd = CommandRequestRW(flen(requests[0].a), flen(requests[0].ba))

		###

		rr = RoundRobin(len(requests), SP_CE)
		self.submodules += rr

		self.comb += [rr.request[i].eq(req.stb & ((req.is_cmd & self.want_cmds) | ((req.is_read == self.want_reads) | (req.is_write == self.want_writes))))
			for i, req in enumerate(requests)]

		stb = Signal()
		self.comb += stb.eq(Array(req.stb for req in requests)[rr.grant])
		for name in ["a", "ba", "is_read", "is_write", "is_cmd"]:
			choices = Array(getattr(req, name) for req in requests)
			self.comb += getattr(self.cmd, name).eq(choices[rr.grant])
		for name in ["cas_n", "ras_n", "we_n"]:
			# we should only assert those signals when stb is 1
			choices = Array(getattr(req, name) for req in requests)
			self.comb += If(self.cmd.stb, getattr(self.cmd, name).eq(choices[rr.grant]))
		self.comb += self.cmd.stb.eq(stb \
			& ((self.cmd.is_cmd & self.want_cmds) | ((self.cmd.is_read == self.want_reads) \
			& (self.cmd.is_write == self.want_writes))))

		self.comb += [If(self.cmd.stb & self.cmd.ack & (rr.grant == i), req.ack.eq(1))
			for i, req in enumerate(requests)]
		self.comb += rr.ce.eq(self.cmd.ack)

USING DATAFLOW:
class _LiteDRAMCommandChooser(Module):
	def __init__(self, bank_cmds):
		self.want_reads = Signal()
		self.want_writes = Signal()
		self.want_cmds = Signal()
		a = flen(bank_cmds[0].a)
		ba = flen(banks_cmds[0]ba)
		self.cmd = Source(dram_bank_cmd_description)
		###

		nbank = len(bank_cmds)

		rr = RoundRobin(nbank, SP_CE)
		mux = Multiplexer(dram_bank_cmd_description(a, ba), nbank)
		self.submodules += rr, mux
		for i, bank_cmd in enumerate(bank_cmds):
			self.comb += [
				rr.request[i].eq(
					bank_cmd.stb &
					(	(bank_cmd.is_cmd & self.want_cmds) |
				 		(bank_cmd.is_read & self.want_reads) |
				 		(bank_cmd.is_write & self.want_writes)
					)
				),
				getattr(mux, "sink"+str(i)).eq(bank_cmd)
			]
		self.comb += rr.ce.eq(self.cmd.stb & self.cmd.ack)