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GMA1
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  1.  
  2. *** Running vivado
  3. with args -log system_wrapper.rdi -applog -m64 -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace
  4.  
  5.  
  6. ****** Vivado v2013.4 (64-bit)
  7. **** SW Build 353583 on Mon Dec 9 17:49:19 MST 2013
  8. **** IP Build 208076 on Mon Dec 2 12:38:17 MST 2013
  9. ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
  10.  
  11. Attempting to get a license: Implementation
  12. INFO: [Common 17-86] Your Implementation license expires in 23 day(s)
  13. Feature available: Implementation
  14. Loading parts and site information from D:/PFE-Install/Vivado/2013.4/data/parts/arch.xml
  15. Parsing RTL primitives file [D:/PFE-Install/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
  16. Finished parsing RTL primitives file [D:/PFE-Install/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
  17. source system_wrapper.tcl -notrace
  18. Design is defaulting to srcset: sources_1
  19. Design is defaulting to constrset: constrs_1
  20. INFO: [Netlist 29-17] Analyzing 32 Unisim elements for replacement
  21. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  22. INFO: [Project 1-479] Netlist was created with Vivado 2013.4
  23. Loading clock regions from D:/PFE-Install/Vivado/2013.4/data\parts/xilinx/zynq/zynq/xc7z020/ClockRegion.xml
  24. Loading clock buffers from D:/PFE-Install/Vivado/2013.4/data\parts/xilinx/zynq/zynq/xc7z020/ClockBuffers.xml
  25. Loading clock placement rules from D:/PFE-Install/Vivado/2013.4/data/parts/xilinx/zynq/ClockPlacerRules.xml
  26. Loading package pin functions from D:/PFE-Install/Vivado/2013.4/data\parts/xilinx/zynq/PinFunctions.xml...
  27. Loading package from D:/PFE-Install/Vivado/2013.4/data\parts/xilinx/zynq/zynq/xc7z020/clg484/Package.xml
  28. Loading io standards from D:/PFE-Install/Vivado/2013.4/data\./parts/xilinx/zynq/IOStandards.xml
  29. INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
  30. INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
  31. Parsing XDC File [d:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
  32. Finished Parsing XDC File [d:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
  33. Parsing XDC File [d:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.srcs/sources_1/bd/system/ip/system_axi_gpio_0_0/system_axi_gpio_0_0.xdc] for cell 'system_i/axi_gpio_0/U0'
  34. Finished Parsing XDC File [d:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.srcs/sources_1/bd/system/ip/system_axi_gpio_0_0/system_axi_gpio_0_0.xdc] for cell 'system_i/axi_gpio_0/U0'
  35. Parsing XDC File [d:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.srcs/sources_1/bd/system/ip/system_axi_gpio_0_0/system_axi_gpio_0_0_board.xdc] for cell 'system_i/axi_gpio_0/U0'
  36. Finished Parsing XDC File [d:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.srcs/sources_1/bd/system/ip/system_axi_gpio_0_0/system_axi_gpio_0_0_board.xdc] for cell 'system_i/axi_gpio_0/U0'
  37. Parsing XDC File [d:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.srcs/sources_1/bd/system/ip/system_rst_processing_system7_0_50M_0/system_rst_processing_system7_0_50M_0.xdc] for cell 'system_i/rst_processing_system7_0_50M/U0'
  38. Finished Parsing XDC File [d:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.srcs/sources_1/bd/system/ip/system_rst_processing_system7_0_50M_0/system_rst_processing_system7_0_50M_0.xdc] for cell 'system_i/rst_processing_system7_0_50M/U0'
  39. Parsing XDC File [d:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.srcs/sources_1/bd/system/ip/system_rst_processing_system7_0_50M_0/system_rst_processing_system7_0_50M_0_board.xdc] for cell 'system_i/rst_processing_system7_0_50M/U0'
  40. Finished Parsing XDC File [d:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.srcs/sources_1/bd/system/ip/system_rst_processing_system7_0_50M_0/system_rst_processing_system7_0_50M_0_board.xdc] for cell 'system_i/rst_processing_system7_0_50M/U0'
  41. Parsing XDC File [D:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.srcs/constrs_1/new/PL_pin.xdc]
  42. Finished Parsing XDC File [D:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.srcs/constrs_1/new/PL_pin.xdc]
  43. Parsing XDC File [D:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.runs/impl_1/.Xil/Vivado-2576-/dcp/system_wrapper.xdc]
  44. Finished Parsing XDC File [D:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.runs/impl_1/.Xil/Vivado-2576-/dcp/system_wrapper.xdc]
  45. INFO: [Opt 31-138] Pushed 0 inverter(s).
  46. INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files:
  47. INFO: [Project 1-111] Unisim Transformation Summary:
  48. A total of 32 instances were transformed.
  49. IOBUF => IOBUF (OBUFT, IBUF): 32 instances
  50.  
  51. link_design: Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 870.211 ; gain = 685.270
  52. Command: opt_design
  53. Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
  54. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
  55. Running DRC as a precondition to command opt_design
  56.  
  57. Starting DRC Task
  58. INFO: [Drc 23-27] Running DRC with 2 threads
  59. INFO: [Project 1-461] DRC finished with 0 Errors
  60. INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
  61.  
  62. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.317 . Memory (MB): peak = 873.160 ; gain = 2.949
  63.  
  64. Starting Logic Optimization Task
  65. INFO: [Timing 38-35] Done setting XDC timing constraints.
  66.  
  67. Phase 1 Retarget
  68.  
  69. INFO: [Opt 31-138] Pushed 0 inverter(s).
  70. INFO: [Opt 31-49] Retargeted 0 cell(s).
  71. Phase 1 Retarget | Checksum: febc22fd
  72.  
  73. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.510 . Memory (MB): peak = 877.820 ; gain = 4.660
  74.  
  75. Phase 2 Constant Propagation
  76. INFO: [Opt 31-138] Pushed 0 inverter(s).
  77. INFO: [Opt 31-10] Eliminated 40 cells.
  78. Phase 2 Constant Propagation | Checksum: 1c4ccb1d6
  79.  
  80. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 877.820 ; gain = 4.660
  81.  
  82. Phase 3 Sweep
  83. INFO: [Opt 31-12] Eliminated 198 unconnected nets.
  84. INFO: [Opt 31-11] Eliminated 259 unconnected cells.
  85. Phase 3 Sweep | Checksum: 1fe945334
  86.  
  87. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 877.820 ; gain = 4.660
  88. Ending Logic Optimization Task | Checksum: 1fe945334
  89.  
  90. Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 877.820 ; gain = 4.660
  91. Implement Debug Cores | Checksum: febc22fd
  92. Logic Optimization | Checksum: febc22fd
  93.  
  94. Starting Power Optimization Task
  95. Ending Power Optimization Task | Checksum: 1fe945334
  96.  
  97. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.086 . Memory (MB): peak = 877.820 ; gain = 0.000
  98. INFO: [Common 17-83] Releasing license: Implementation
  99. 20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  100. opt_design completed successfully
  101. INFO: [Timing 38-35] Done setting XDC timing constraints.
  102. Writing XDEF routing.
  103. Writing XDEF routing logical nets.
  104. Writing XDEF routing special nets.
  105. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.270 . Memory (MB): peak = 879.438 ; gain = 0.000
  106. Command: place_design
  107. Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
  108. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
  109. Running DRC as a precondition to command place_design
  110. INFO: [Drc 23-27] Running DRC with 2 threads
  111. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  112. INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  113.  
  114. Starting Placer Task
  115. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
  116.  
  117. Phase 1 Placer Initialization
  118.  
  119. Phase 1.1 Placer Initialization Core
  120. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 881.684 ; gain = 0.000
  121.  
  122. Phase 1.1.1 Mandatory Logic Optimization
  123. INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
  124. INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
  125. INFO: [Opt 31-138] Pushed 0 inverter(s).
  126. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 881.684 ; gain = 0.000
  127. Phase 1.1.1 Mandatory Logic Optimization | Checksum: bec50440
  128.  
  129. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.310 . Memory (MB): peak = 881.684 ; gain = 0.000
  130.  
  131. Phase 1.1.2 Build Super Logic Region (SLR) Database
  132. Phase 1.1.2 Build Super Logic Region (SLR) Database | Checksum: bec50440
  133.  
  134. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.356 . Memory (MB): peak = 881.684 ; gain = 0.000
  135.  
  136. Phase 1.1.3 Add Constraints
  137. Phase 1.1.3 Add Constraints | Checksum: bec50440
  138.  
  139. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.361 . Memory (MB): peak = 881.684 ; gain = 0.000
  140.  
  141. Phase 1.1.4 Build Macros
  142. Phase 1.1.4 Build Macros | Checksum: 19c4b338a
  143.  
  144. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.896 . Memory (MB): peak = 881.684 ; gain = 0.000
  145.  
  146. Phase 1.1.5 Implementation Feasibility check
  147. WARNING: [Place 30-87] Partially locked IO Bus is found. Following components of the IO Bus led_dutycycle_tri_io are not locked: 'led_dutycycle_tri_io[8]' 'led_dutycycle_tri_io[9]' 'led_dutycycle_tri_io[10]' 'led_dutycycle_tri_io[11]' 'led_dutycycle_tri_io[12]' 'led_dutycycle_tri_io[13]' 'led_dutycycle_tri_io[14]' 'led_dutycycle_tri_io[15]' 'led_dutycycle_tri_io[16]' 'led_dutycycle_tri_io[17]' 'led_dutycycle_tri_io[18]' 'led_dutycycle_tri_io[19]' 'led_dutycycle_tri_io[20]' 'led_dutycycle_tri_io[21]' 'led_dutycycle_tri_io[22]' 'led_dutycycle_tri_io[23]' 'led_dutycycle_tri_io[24]' 'led_dutycycle_tri_io[25]' 'led_dutycycle_tri_io[26]' 'led_dutycycle_tri_io[27]' 'led_dutycycle_tri_io[28]' 'led_dutycycle_tri_io[29]' 'led_dutycycle_tri_io[30]' 'led_dutycycle_tri_io[31]'
  148. WARNING: [Place 30-12] An IO Bus FIXED_IO_mio with more than one IO standard is found. Components associated with this bus are:
  149. FIXED_IO_mio[0] of IOStandard LVCMOS33
  150. FIXED_IO_mio[1] of IOStandard LVCMOS33
  151. FIXED_IO_mio[2] of IOStandard LVCMOS33
  152. FIXED_IO_mio[3] of IOStandard LVCMOS33
  153. FIXED_IO_mio[4] of IOStandard LVCMOS33
  154. FIXED_IO_mio[5] of IOStandard LVCMOS33
  155. FIXED_IO_mio[6] of IOStandard LVCMOS33
  156. FIXED_IO_mio[7] of IOStandard LVCMOS33
  157. FIXED_IO_mio[8] of IOStandard LVCMOS33
  158. FIXED_IO_mio[9] of IOStandard LVCMOS33
  159. FIXED_IO_mio[10] of IOStandard LVCMOS33
  160. FIXED_IO_mio[11] of IOStandard LVCMOS33
  161. FIXED_IO_mio[12] of IOStandard LVCMOS33
  162. FIXED_IO_mio[13] of IOStandard LVCMOS33
  163. FIXED_IO_mio[14] of IOStandard LVCMOS33
  164. FIXED_IO_mio[15] of IOStandard LVCMOS33
  165. FIXED_IO_mio[16] of IOStandard LVCMOS18
  166. FIXED_IO_mio[17] of IOStandard LVCMOS18
  167. FIXED_IO_mio[18] of IOStandard LVCMOS18
  168. FIXED_IO_mio[19] of IOStandard LVCMOS18
  169. FIXED_IO_mio[20] of IOStandard LVCMOS18
  170. FIXED_IO_mio[21] of IOStandard LVCMOS18
  171. FIXED_IO_mio[22] of IOStandard LVCMOS18
  172. FIXED_IO_mio[23] of IOStandard LVCMOS18
  173. FIXED_IO_mio[24] of IOStandard LVCMOS18
  174. FIXED_IO_mio[25] of IOStandard LVCMOS18
  175. FIXED_IO_mio[26] of IOStandard LVCMOS18
  176. FIXED_IO_mio[27] of IOStandard LVCMOS18
  177. FIXED_IO_mio[28] of IOStandard LVCMOS18
  178. FIXED_IO_mio[29] of IOStandard LVCMOS18
  179. FIXED_IO_mio[30] of IOStandard LVCMOS18
  180. FIXED_IO_mio[31] of IOStandard LVCMOS18
  181. FIXED_IO_mio[32] of IOStandard LVCMOS18
  182. FIXED_IO_mio[33] of IOStandard LVCMOS18
  183. FIXED_IO_mio[34] of IOStandard LVCMOS18
  184. FIXED_IO_mio[35] of IOStandard LVCMOS18
  185. FIXED_IO_mio[36] of IOStandard LVCMOS18
  186. FIXED_IO_mio[37] of IOStandard LVCMOS18
  187. FIXED_IO_mio[38] of IOStandard LVCMOS18
  188. FIXED_IO_mio[39] of IOStandard LVCMOS18
  189. FIXED_IO_mio[40] of IOStandard LVCMOS18
  190. FIXED_IO_mio[41] of IOStandard LVCMOS18
  191. FIXED_IO_mio[42] of IOStandard LVCMOS18
  192. FIXED_IO_mio[43] of IOStandard LVCMOS18
  193. FIXED_IO_mio[44] of IOStandard LVCMOS18
  194. FIXED_IO_mio[45] of IOStandard LVCMOS18
  195. FIXED_IO_mio[46] of IOStandard LVCMOS18
  196. FIXED_IO_mio[47] of IOStandard LVCMOS18
  197. FIXED_IO_mio[48] of IOStandard LVCMOS18
  198. FIXED_IO_mio[49] of IOStandard LVCMOS18
  199. FIXED_IO_mio[50] of IOStandard LVCMOS18
  200. FIXED_IO_mio[51] of IOStandard LVCMOS18
  201. FIXED_IO_mio[52] of IOStandard LVCMOS18
  202. FIXED_IO_mio[53] of IOStandard LVCMOS18
  203. WARNING: [Place 30-12] An IO Bus led_dutycycle_tri_io with more than one IO standard is found. Components associated with this bus are:
  204. led_dutycycle_tri_io[0] of IOStandard LVCMOS33
  205. led_dutycycle_tri_io[1] of IOStandard LVCMOS33
  206. led_dutycycle_tri_io[2] of IOStandard LVCMOS33
  207. led_dutycycle_tri_io[3] of IOStandard LVCMOS33
  208. led_dutycycle_tri_io[4] of IOStandard LVCMOS33
  209. led_dutycycle_tri_io[5] of IOStandard LVCMOS33
  210. led_dutycycle_tri_io[6] of IOStandard LVCMOS33
  211. led_dutycycle_tri_io[7] of IOStandard LVCMOS33
  212. led_dutycycle_tri_io[8] of IOStandard LVCMOS18
  213. led_dutycycle_tri_io[9] of IOStandard LVCMOS18
  214. led_dutycycle_tri_io[10] of IOStandard LVCMOS18
  215. led_dutycycle_tri_io[11] of IOStandard LVCMOS18
  216. led_dutycycle_tri_io[12] of IOStandard LVCMOS18
  217. led_dutycycle_tri_io[13] of IOStandard LVCMOS18
  218. led_dutycycle_tri_io[14] of IOStandard LVCMOS18
  219. led_dutycycle_tri_io[15] of IOStandard LVCMOS18
  220. led_dutycycle_tri_io[16] of IOStandard LVCMOS18
  221. led_dutycycle_tri_io[17] of IOStandard LVCMOS18
  222. led_dutycycle_tri_io[18] of IOStandard LVCMOS18
  223. led_dutycycle_tri_io[19] of IOStandard LVCMOS18
  224. led_dutycycle_tri_io[20] of IOStandard LVCMOS18
  225. led_dutycycle_tri_io[21] of IOStandard LVCMOS18
  226. led_dutycycle_tri_io[22] of IOStandard LVCMOS18
  227. led_dutycycle_tri_io[23] of IOStandard LVCMOS18
  228. led_dutycycle_tri_io[24] of IOStandard LVCMOS18
  229. led_dutycycle_tri_io[25] of IOStandard LVCMOS18
  230. led_dutycycle_tri_io[26] of IOStandard LVCMOS18
  231. led_dutycycle_tri_io[27] of IOStandard LVCMOS18
  232. led_dutycycle_tri_io[28] of IOStandard LVCMOS18
  233. led_dutycycle_tri_io[29] of IOStandard LVCMOS18
  234. led_dutycycle_tri_io[30] of IOStandard LVCMOS18
  235. led_dutycycle_tri_io[31] of IOStandard LVCMOS18
  236. Phase 1.1.5 Implementation Feasibility check | Checksum: 19c4b338a
  237.  
  238. Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 881.684 ; gain = 0.000
  239.  
  240. Phase 1.1.6 Pre-Place Cells
  241. Phase 1.1.6 Pre-Place Cells | Checksum: 19c4b338a
  242.  
  243. Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 881.684 ; gain = 0.000
  244.  
  245. Phase 1.1.7 IO Placement/ Clock Placement/ Build Placer Device
  246. Phase 1.1.7 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1afbafedb
  247.  
  248. Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 885.328 ; gain = 3.645
  249.  
  250. Phase 1.1.8 Build Placer Netlist Model
  251.  
  252. Phase 1.1.8.1 Place Init Design
  253.  
  254. Phase 1.1.8.1.1 Build Clock Data
  255. Phase 1.1.8.1.1 Build Clock Data | Checksum: 23bd41232
  256.  
  257. Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 885.535 ; gain = 3.852
  258. Phase 1.1.8.1 Place Init Design | Checksum: 298fc207e
  259.  
  260. Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 885.535 ; gain = 3.852
  261. Phase 1.1.8 Build Placer Netlist Model | Checksum: 298fc207e
  262.  
  263. Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 885.535 ; gain = 3.852
  264.  
  265. Phase 1.1.9 Constrain Clocks/Macros
  266.  
  267. Phase 1.1.9.1 Constrain Global/Regional Clocks
  268. Phase 1.1.9.1 Constrain Global/Regional Clocks | Checksum: 298fc207e
  269.  
  270. Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 885.535 ; gain = 3.852
  271. Phase 1.1.9 Constrain Clocks/Macros | Checksum: 298fc207e
  272.  
  273. Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 885.535 ; gain = 3.852
  274. Phase 1.1 Placer Initialization Core | Checksum: 298fc207e
  275.  
  276. Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 885.535 ; gain = 3.852
  277. Phase 1 Placer Initialization | Checksum: 298fc207e
  278.  
  279. Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 885.535 ; gain = 3.852
  280.  
  281. Phase 2 Global Placement
  282.  
  283. Phase 2.1 Run Budgeter
  284. Phase 2.1 Run Budgeter | Checksum: 2742aaded
  285.  
  286. Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 891.207 ; gain = 9.523
  287. Phase 2 Global Placement | Checksum: 1ee225f38
  288.  
  289. Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 891.207 ; gain = 9.523
  290.  
  291. Phase 3 Detail Placement
  292.  
  293. Phase 3.1 Commit Multi Column Macros
  294. Phase 3.1 Commit Multi Column Macros | Checksum: 1ee225f38
  295.  
  296. Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 891.207 ; gain = 9.523
  297.  
  298. Phase 3.2 Commit Most Macros & LUTRAMs
  299. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1e05dbfd9
  300.  
  301. Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 898.668 ; gain = 16.984
  302.  
  303. Phase 3.3 Area Swap Optimization
  304. Phase 3.3 Area Swap Optimization | Checksum: 25b987547
  305.  
  306. Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 898.668 ; gain = 16.984
  307.  
  308. Phase 3.4 Timing Path Optimizer
  309. Phase 3.4 Timing Path Optimizer | Checksum: 2a7a6d0f8
  310.  
  311. Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 899.840 ; gain = 18.156
  312.  
  313. Phase 3.5 Commit Small Macros & Core Logic
  314. Phase 3.5 Commit Small Macros & Core Logic | Checksum: 227e8fa72
  315.  
  316. Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 904.504 ; gain = 22.820
  317.  
  318. Phase 3.6 Re-assign LUT pins
  319. Phase 3.6 Re-assign LUT pins | Checksum: 227e8fa72
  320.  
  321. Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 904.504 ; gain = 22.820
  322. Phase 3 Detail Placement | Checksum: 227e8fa72
  323.  
  324. Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 904.504 ; gain = 22.820
  325.  
  326. Phase 4 Post Placement Optimization and Clean-Up
  327.  
  328. Phase 4.1 PCOPT Shape updates
  329. Phase 4.1 PCOPT Shape updates | Checksum: 1c9c45e9c
  330.  
  331. Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 904.504 ; gain = 22.820
  332.  
  333. Phase 4.2 Post Placement Optimization
  334.  
  335. Phase 4.2.1 Post Placement Timing Optimization
  336. Phase 4.2.1 Post Placement Timing Optimization | Checksum: 28d4ed44a
  337.  
  338. Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 904.504 ; gain = 22.820
  339. Phase 4.2 Post Placement Optimization | Checksum: 28d4ed44a
  340.  
  341. Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 904.504 ; gain = 22.820
  342.  
  343. Phase 4.3 Post Placement Cleanup
  344. Phase 4.3 Post Placement Cleanup | Checksum: 28d4ed44a
  345.  
  346. Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 904.504 ; gain = 22.820
  347.  
  348. Phase 4.4 Placer Reporting
  349.  
  350. Phase 4.4.1 Congestion Reporting
  351. Phase 4.4.1 Congestion Reporting | Checksum: 28d4ed44a
  352.  
  353. Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 904.504 ; gain = 22.820
  354.  
  355. Phase 4.4.2 updateTiming final
  356. Phase 4.4.2 updateTiming final | Checksum: 2afdbb91e
  357.  
  358. Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 904.504 ; gain = 22.820
  359.  
  360. Phase 4.4.3 Dump Critical Paths
  361. Phase 4.4.3 Dump Critical Paths | Checksum: 2afdbb91e
  362.  
  363. Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 904.504 ; gain = 22.820
  364.  
  365. Phase 4.4.4 Restore STA
  366. Phase 4.4.4 Restore STA | Checksum: 2afdbb91e
  367.  
  368. Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 904.504 ; gain = 22.820
  369.  
  370. Phase 4.4.5 Print Final WNS
  371. INFO: [Place 30-100] Post Placement Timing Summary | WNS=12.642 | TNS=0.000 |
  372.  
  373. Phase 4.4.5 Print Final WNS | Checksum: 2afdbb91e
  374.  
  375. Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 904.504 ; gain = 22.820
  376. Phase 4.4 Placer Reporting | Checksum: 2afdbb91e
  377.  
  378. Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 904.504 ; gain = 22.820
  379.  
  380. Phase 4.5 Final Placement Cleanup
  381. Phase 4.5 Final Placement Cleanup | Checksum: 23fd4de08
  382.  
  383. Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 904.504 ; gain = 22.820
  384. Phase 4 Post Placement Optimization and Clean-Up | Checksum: 23fd4de08
  385.  
  386. Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 904.504 ; gain = 22.820
  387. Ending Placer Task | Checksum: 154f79254
  388.  
  389. Time (s): cpu = 00:00:00 ; elapsed = 00:00:13 . Memory (MB): peak = 904.504 ; gain = 22.820
  390. INFO: [Common 17-83] Releasing license: Implementation
  391. 31 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
  392. place_design completed successfully
  393. place_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 904.504 ; gain = 25.066
  394. INFO: [Timing 38-163] DEBUG : Generate clock report | CPU: 0 secs
  395.  
  396. report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 906.809 ; gain = 0.000
  397. INFO: [Designutils 20-134] DEBUG : Generate Control Sets report | CPU: 0 secs
  398. Writing XDEF routing.
  399. Writing XDEF routing logical nets.
  400. Writing XDEF routing special nets.
  401. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.381 . Memory (MB): peak = 906.809 ; gain = 0.000
  402. Command: route_design
  403. Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
  404. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
  405. Running DRC as a precondition to command route_design
  406. INFO: [Drc 23-27] Running DRC with 2 threads
  407. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 3 Warnings
  408. INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  409.  
  410.  
  411. Starting Routing Task
  412. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
  413.  
  414. Starting Route Task
  415.  
  416. Phase 1 Build RT Design
  417.  
  418. Phase 1.1 Build Netlist & NodeGraph
  419. Phase 1.1 Build Netlist & NodeGraph | Checksum: 154f79254
  420.  
  421. Time (s): cpu = 00:02:17 ; elapsed = 00:01:03 . Memory (MB): peak = 1051.848 ; gain = 128.340
  422. Phase 1 Build RT Design | Checksum: 15c52eb8c
  423.  
  424. Time (s): cpu = 00:02:17 ; elapsed = 00:01:04 . Memory (MB): peak = 1051.848 ; gain = 128.340
  425.  
  426. Phase 2 Router Initialization
  427.  
  428. Phase 2.1 Create Timer
  429. Phase 2.1 Create Timer | Checksum: 15c52eb8c
  430.  
  431. Time (s): cpu = 00:02:17 ; elapsed = 00:01:04 . Memory (MB): peak = 1051.848 ; gain = 128.340
  432.  
  433. Phase 2.2 Restore Routing
  434. Phase 2.2 Restore Routing | Checksum: 15c52eb8c
  435.  
  436. Time (s): cpu = 00:02:18 ; elapsed = 00:01:04 . Memory (MB): peak = 1060.168 ; gain = 136.660
  437.  
  438. Phase 2.3 Special Net Routing
  439. Number of Nodes with overlaps = 0
  440. Phase 2.3 Special Net Routing | Checksum: c805c552
  441.  
  442. Time (s): cpu = 00:02:18 ; elapsed = 00:01:05 . Memory (MB): peak = 1076.016 ; gain = 152.508
  443.  
  444. Phase 2.4 Local Clock Net Routing
  445. Phase 2.4 Local Clock Net Routing | Checksum: c805c552
  446.  
  447. Time (s): cpu = 00:02:18 ; elapsed = 00:01:05 . Memory (MB): peak = 1076.016 ; gain = 152.508
  448.  
  449. Phase 2.5 Update Timing
  450.  
  451. Phase 2.5.1 Update timing with NCN CRPR
  452.  
  453. Phase 2.5.1.1 Hold Budgeting
  454. Phase 2.5.1.1 Hold Budgeting | Checksum: c805c552
  455.  
  456. Time (s): cpu = 00:02:19 ; elapsed = 00:01:06 . Memory (MB): peak = 1076.016 ; gain = 152.508
  457. Phase 2.5.1 Update timing with NCN CRPR | Checksum: c805c552
  458.  
  459. Time (s): cpu = 00:02:19 ; elapsed = 00:01:06 . Memory (MB): peak = 1076.016 ; gain = 152.508
  460. Phase 2.5 Update Timing | Checksum: c805c552
  461.  
  462. Time (s): cpu = 00:02:19 ; elapsed = 00:01:06 . Memory (MB): peak = 1076.016 ; gain = 152.508
  463. INFO: [Route 35-57] Estimated Timing Summary | WNS=12.8 | TNS=0 | WHS=-0.186 | THS=-17.7 |
  464.  
  465.  
  466. Phase 2.6 Budgeting
  467. Phase 2.6 Budgeting | Checksum: c805c552
  468.  
  469. Time (s): cpu = 00:02:20 ; elapsed = 00:01:06 . Memory (MB): peak = 1076.016 ; gain = 152.508
  470. Phase 2 Router Initialization | Checksum: c805c552
  471.  
  472. Time (s): cpu = 00:02:20 ; elapsed = 00:01:06 . Memory (MB): peak = 1076.016 ; gain = 152.508
  473.  
  474. Phase 3 Initial Routing
  475. Phase 3 Initial Routing | Checksum: 5c01e538
  476.  
  477. Time (s): cpu = 00:02:20 ; elapsed = 00:01:06 . Memory (MB): peak = 1076.016 ; gain = 152.508
  478.  
  479. Phase 4 Rip-up And Reroute
  480.  
  481. Phase 4.1 Global Iteration 0
  482.  
  483. Phase 4.1.1 Remove Overlaps
  484. Number of Nodes with overlaps = 70
  485. Number of Nodes with overlaps = 0
  486. Phase 4.1.1 Remove Overlaps | Checksum: 1ea5a4e91
  487.  
  488. Time (s): cpu = 00:02:21 ; elapsed = 00:01:07 . Memory (MB): peak = 1076.016 ; gain = 152.508
  489.  
  490. Phase 4.1.2 Update Timing
  491. Phase 4.1.2 Update Timing | Checksum: 1ea5a4e91
  492.  
  493. Time (s): cpu = 00:02:21 ; elapsed = 00:01:07 . Memory (MB): peak = 1076.016 ; gain = 152.508
  494. INFO: [Route 35-57] Estimated Timing Summary | WNS=10.1 | TNS=0 | WHS=N/A | THS=N/A |
  495.  
  496.  
  497. Phase 4.1.3 collectNewHoldAndFix
  498. Phase 4.1.3 collectNewHoldAndFix | Checksum: 174deab09
  499.  
  500. Time (s): cpu = 00:02:21 ; elapsed = 00:01:07 . Memory (MB): peak = 1076.016 ; gain = 152.508
  501. Phase 4.1 Global Iteration 0 | Checksum: 174deab09
  502.  
  503. Time (s): cpu = 00:02:22 ; elapsed = 00:01:07 . Memory (MB): peak = 1076.016 ; gain = 152.508
  504.  
  505. Phase 4.2 Global Iteration 1
  506.  
  507. Phase 4.2.1 Remove Overlaps
  508. Number of Nodes with overlaps = 2
  509. Number of Nodes with overlaps = 0
  510. Phase 4.2.1 Remove Overlaps | Checksum: b286c113
  511.  
  512. Time (s): cpu = 00:02:22 ; elapsed = 00:01:07 . Memory (MB): peak = 1076.016 ; gain = 152.508
  513.  
  514. Phase 4.2.2 Update Timing
  515. Phase 4.2.2 Update Timing | Checksum: b286c113
  516.  
  517. Time (s): cpu = 00:02:22 ; elapsed = 00:01:07 . Memory (MB): peak = 1076.016 ; gain = 152.508
  518. INFO: [Route 35-57] Estimated Timing Summary | WNS=10.1 | TNS=0 | WHS=N/A | THS=N/A |
  519.  
  520.  
  521. Phase 4.2.3 collectNewHoldAndFix
  522. Phase 4.2.3 collectNewHoldAndFix | Checksum: b286c113
  523.  
  524. Time (s): cpu = 00:02:22 ; elapsed = 00:01:07 . Memory (MB): peak = 1076.016 ; gain = 152.508
  525. Phase 4.2 Global Iteration 1 | Checksum: b286c113
  526.  
  527. Time (s): cpu = 00:02:22 ; elapsed = 00:01:07 . Memory (MB): peak = 1076.016 ; gain = 152.508
  528. Phase 4 Rip-up And Reroute | Checksum: b286c113
  529.  
  530. Time (s): cpu = 00:02:22 ; elapsed = 00:01:07 . Memory (MB): peak = 1076.016 ; gain = 152.508
  531.  
  532. Phase 5 Delay CleanUp
  533.  
  534. Phase 5.1 Update Timing
  535. Phase 5.1 Update Timing | Checksum: b286c113
  536.  
  537. Time (s): cpu = 00:02:22 ; elapsed = 00:01:07 . Memory (MB): peak = 1076.016 ; gain = 152.508
  538. INFO: [Route 35-57] Estimated Timing Summary | WNS=10.1 | TNS=0 | WHS=N/A | THS=N/A |
  539.  
  540. Phase 5 Delay CleanUp | Checksum: b286c113
  541.  
  542. Time (s): cpu = 00:02:22 ; elapsed = 00:01:07 . Memory (MB): peak = 1076.016 ; gain = 152.508
  543.  
  544. Phase 6 Post Hold Fix
  545.  
  546. Phase 6.1 Full Hold Analysis
  547.  
  548. Phase 6.1.1 Update Timing
  549. Phase 6.1.1 Update Timing | Checksum: b286c113
  550.  
  551. Time (s): cpu = 00:02:22 ; elapsed = 00:01:08 . Memory (MB): peak = 1076.016 ; gain = 152.508
  552. INFO: [Route 35-57] Estimated Timing Summary | WNS=10.1 | TNS=0 | WHS=0.048 | THS=0 |
  553.  
  554. Phase 6.1 Full Hold Analysis | Checksum: b286c113
  555.  
  556. Time (s): cpu = 00:02:22 ; elapsed = 00:01:08 . Memory (MB): peak = 1076.016 ; gain = 152.508
  557. Phase 6 Post Hold Fix | Checksum: b286c113
  558.  
  559. Time (s): cpu = 00:02:22 ; elapsed = 00:01:08 . Memory (MB): peak = 1076.016 ; gain = 152.508
  560.  
  561. Router Utilization Summary
  562. Global Vertical Routing Utilization = 0.454178 %
  563. Global Horizontal Routing Utilization = 0.414638 %
  564. Routable Net Status*
  565. *Does not include unroutable nets such as driverless and loadless.
  566. Run report_route_status for detailed report.
  567. Number of Failed Nets = 0
  568. Number of Unrouted Nets = 0
  569. Number of Partially Routed Nets = 0
  570. Number of Node Overlaps = 0
  571.  
  572.  
  573. Phase 7 Verifying routed nets
  574.  
  575. Verification completed successfully
  576. Phase 7 Verifying routed nets | Checksum: b286c113
  577.  
  578. Time (s): cpu = 00:02:22 ; elapsed = 00:01:08 . Memory (MB): peak = 1076.016 ; gain = 152.508
  579.  
  580. Phase 8 Depositing Routes
  581. Phase 8 Depositing Routes | Checksum: dde90d43
  582.  
  583. Time (s): cpu = 00:02:23 ; elapsed = 00:01:08 . Memory (MB): peak = 1076.016 ; gain = 152.508
  584.  
  585. Phase 9 Post Router Timing
  586. INFO: [Route 35-20] Post Routing Timing Summary | WNS=10.116 | TNS=0.000 | WHS=0.049 | THS=0.000 |
  587.  
  588. INFO: [Route 35-61] The design met the timing requirement.
  589. Phase 9 Post Router Timing | Checksum: dde90d43
  590.  
  591. Time (s): cpu = 00:02:26 ; elapsed = 00:01:10 . Memory (MB): peak = 1076.016 ; gain = 152.508
  592. INFO: [Route 35-16] Router Completed Successfully
  593. Ending Route Task | Checksum: dde90d43
  594.  
  595. Time (s): cpu = 00:00:00 ; elapsed = 00:01:10 . Memory (MB): peak = 1076.016 ; gain = 152.508
  596.  
  597. Routing Is Done.
  598.  
  599. Time (s): cpu = 00:00:00 ; elapsed = 00:01:10 . Memory (MB): peak = 1076.016 ; gain = 152.508
  600. INFO: [Common 17-83] Releasing license: Implementation
  601. 47 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
  602. route_design completed successfully
  603. route_design: Time (s): cpu = 00:02:27 ; elapsed = 00:01:12 . Memory (MB): peak = 1076.016 ; gain = 169.207
  604. INFO: [Drc 23-27] Running DRC with 2 threads
  605. INFO: [Coretcl 2-168] The results of DRC are in file D:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.runs/impl_1/system_wrapper_drc_routed.rpt.
  606. Running Vector-less Activity Propagation...
  607.  
  608. Finished Running Vector-less Activity Propagation
  609. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Constraints type: SDC.
  610. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
  611. Writing XDEF routing.
  612. Writing XDEF routing logical nets.
  613. Writing XDEF routing special nets.
  614. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.474 . Memory (MB): peak = 1076.016 ; gain = 0.000
  615. INFO: [Common 17-206] Exiting Vivado at Wed Apr 16 11:46:07 2014...
  616.  
  617. *** Running vivado
  618. with args -log system_wrapper.rdi -applog -m64 -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace
  619.  
  620.  
  621. ****** Vivado v2013.4 (64-bit)
  622. **** SW Build 353583 on Mon Dec 9 17:49:19 MST 2013
  623. **** IP Build 208076 on Mon Dec 2 12:38:17 MST 2013
  624. ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
  625.  
  626. Attempting to get a license: Implementation
  627. INFO: [Common 17-86] Your Implementation license expires in 23 day(s)
  628. Feature available: Implementation
  629. Loading parts and site information from D:/PFE-Install/Vivado/2013.4/data/parts/arch.xml
  630. Parsing RTL primitives file [D:/PFE-Install/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
  631. Finished parsing RTL primitives file [D:/PFE-Install/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
  632. source system_wrapper.tcl -notrace
  633. Command: open_checkpoint system_wrapper_routed.dcp
  634. INFO: [Netlist 29-17] Analyzing 32 Unisim elements for replacement
  635. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  636. INFO: [Project 1-479] Netlist was created with Vivado 2013.4
  637. Loading clock regions from D:/PFE-Install/Vivado/2013.4/data\parts/xilinx/zynq/zynq/xc7z020/ClockRegion.xml
  638. Loading clock buffers from D:/PFE-Install/Vivado/2013.4/data\parts/xilinx/zynq/zynq/xc7z020/ClockBuffers.xml
  639. Loading clock placement rules from D:/PFE-Install/Vivado/2013.4/data/parts/xilinx/zynq/ClockPlacerRules.xml
  640. Loading package pin functions from D:/PFE-Install/Vivado/2013.4/data\parts/xilinx/zynq/PinFunctions.xml...
  641. Loading package from D:/PFE-Install/Vivado/2013.4/data\parts/xilinx/zynq/zynq/xc7z020/clg484/Package.xml
  642. Loading io standards from D:/PFE-Install/Vivado/2013.4/data\./parts/xilinx/zynq/IOStandards.xml
  643. Parsing XDC File [D:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.runs/impl_1/.Xil/Vivado-7836-/dcp/system_wrapper.xdc]
  644. Finished Parsing XDC File [D:/PFE-Install/Vivado/2013.4/examples/Vivado_Tutorial/Projects/LED/LED.runs/impl_1/.Xil/Vivado-7836-/dcp/system_wrapper.xdc]
  645. Reading XDEF placement.
  646. Reading XDEF routing.
  647. Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.192 . Memory (MB): peak = 869.305 ; gain = 0.000
  648. Restoring placement.
  649. Restored 519 out of 519 XDEF sites from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
  650. INFO: [Opt 31-138] Pushed 0 inverter(s).
  651. INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files:
  652. INFO: [Project 1-111] Unisim Transformation Summary:
  653. A total of 32 instances were transformed.
  654. IOBUF => IOBUF (OBUFT, IBUF): 32 instances
  655.  
  656. INFO: [Project 1-484] Checkpoint was created with build 353583
  657. open_checkpoint: Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 870.168 ; gain = 685.160
  658. Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
  659. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
  660. Running DRC as a precondition to command write_bitstream
  661. INFO: [Drc 23-27] Running DRC with 2 threads
  662. ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 24 out of 163 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led_dutycycle_tri_io[31], led_dutycycle_tri_io[30], led_dutycycle_tri_io[29], led_dutycycle_tri_io[28], led_dutycycle_tri_io[27], led_dutycycle_tri_io[26], led_dutycycle_tri_io[25], led_dutycycle_tri_io[24], led_dutycycle_tri_io[23], led_dutycycle_tri_io[22], led_dutycycle_tri_io[21], led_dutycycle_tri_io[20], led_dutycycle_tri_io[19], led_dutycycle_tri_io[18], led_dutycycle_tri_io[17] (the first 15 of 24 listed).
  663. ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 25 out of 163 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led_dutycycle_tri_io[31], led_dutycycle_tri_io[30], led_dutycycle_tri_io[29], led_dutycycle_tri_io[28], led_dutycycle_tri_io[27], led_dutycycle_tri_io[26], led_dutycycle_tri_io[25], led_dutycycle_tri_io[24], led_dutycycle_tri_io[23], led_dutycycle_tri_io[22], led_dutycycle_tri_io[21], led_dutycycle_tri_io[20], led_dutycycle_tri_io[19], led_dutycycle_tri_io[18], led_dutycycle_tri_io[17] (the first 15 of 25 listed).
  664. INFO: [Vivado 12-3199] DRC finished with 2 Errors, 131 Warnings, 1 Advisories
  665. INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
  666. ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
  667. INFO: [Common 17-83] Releasing license: Implementation
  668. ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.
  669.  
  670. while executing
  671. "write_bitstream -force system_wrapper.bit "
  672. INFO: [Common 17-206] Exiting Vivado at Wed Apr 16 11:47:06 2014...
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