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-- Company:
-- Engineer:
--
-- Create Date: 11/25/2015 03:03:03 PM
-- Design Name:
-- Module Name: Screen_Write - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Screen_Write is
    Port ( CLK : in STD_LOGIC;
           X : in STD_LOGIC;
           Y : in STD_LOGIC;
           VISIBLE : in STD_LOGIC;
           DE : out STD_LOGIC; --Display Enable enkel hoog wanneer visible
           RED : out STD_LOGIC_VECTOR(7 downto 0);
           BLUE : out STD_LOGIC_VECTOR(5 downto 0);
           GREEN : out STD_LOGIC_VECTOR(7 downto 2));
end Screen_Write;

architecture Behavioral of Screen_Write is

component H_SYNC is
    Port ();
end component;

component V_SYNC is
    Port ();
end component

begin
h_sync_proc: H_SYNC port map (
v_sync_proc: V_SYNC port map (
draw_background: process(VISIBLE)
    begin
    if (VISIBLE = 0) then --Outside of the visible screen, draw black
        RED <= "00000000";
        BLUE <= "000000";
        GREEN <= "000000";
    end if;
end process

draw_square: process(VISIBLE, X, Y)
    variable X1 : integer range 1 to 480 := 120;
    variable Y1 : integer range 1 to 272 := 68;
    variable X2 : integer range 1 to 480 := 360;
    variable Y2 : integer range 1 to 272 : 204;
    begin
    if(VISIBLE = 1)
        if ((X > (X1-1) and X < (X2+1))
            and (Y > (Y1-1) and Y < (Y2+1))) then
            RED <= "11111111";
            BLUE <= "000000";
            GREEN <= "000000";

        else
            RED <= "11111111";
            BLUE <= "111111";
            GREEN <= "111111";
        end if;
    end if;


end Behavioral;