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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- ENTITY fsm_C IS
- PORT (
- key: in integer range 0 to 255;
- clk: in std_logic;
- number: out integer range -1000000000 to 1000000000;
- memPos: out integer range 0 to 31;
- ff_write, ff_calc: out std_logic
- );
- END fsm_C;
- ARCHITECTURE fsm_C of fsm_C IS
- signal state: integer range 0 to 7 := 0;
- signal memory: integer range 0 to 31 := 0;
- signal last_key: integer range 0 to 255 := 0;
- signal neg: std_logic := '0';
- signal n, degree: integer range -1000000000 to 1000000000 := 0;
- BEGIN
- PROCESS (clk, key)
- BEGIN
- IF (clk'event AND clk = '1') THEN
- CASE state IS
- WHEN 0 =>
- IF (last_key /= key) THEN
- IF (key = 45) THEN
- state <= 1;
- ELSIF (key >= 48 AND key <= 57) THEN
- state <= 2;
- ELSIF (key = 10) THEN
- IF (neg = '0') THEN
- state <= 3;
- ELSE
- state <= 4;
- END IF;
- END IF;
- last_key <= key;
- END IF;
- WHEN 1 =>
- neg <= '1';
- state <= 0;
- WHEN 2 =>
- n <= (n * 10) + key - 48;
- state <= 0;
- WHEN 3 =>
- ff_write <= '1';
- state <= 5;
- WHEN 4 =>
- n <= (-1) * n;
- state <= 3;
- WHEN 5 =>
- IF (memory = 0) THEN
- degree <= n;
- END IF;
- ff_write <= '0';
- neg <= '0';
- n <= 0;
- memory <= memory + 1;
- IF (memory <= degree) THEN
- state <= 0;
- ELSE
- state <= 6;
- END IF;
- WHEN 6 =>
- ff_calc <= '1';
- state <= 7;
- WHEN 7 =>
- memory <= 0;
- ff_calc <= '0';
- END CASE;
- END IF;
- memPos <= memory;
- number <= n;
- END PROCESS;
- END fsm_C;
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