library ieee;
use ieee.std_logic_1164.all;

entity cmp2 is
        port (
          clk : in std_logic; -- тактовый сигнал
          a1, a0: in std_logic; -- биты первого числа
              b1, b0: in std_logic; -- биты второго числа
              ext_e, ext_g, ext_l: in std_logic; -- входы увеличения разрядности
              e: out std_logic;  -- equal
              g: out std_logic;  -- greater
              l: out std_logic); -- less
end cmp2;

architecture logic of cmp2 is
begin
        process (clk)
                variable e1: std_logic;
        begin
        if rising_edge(clk) then
                    e1 := not (a1 xor b1);
                    e <= ext_e and e1 and (not (a0 xor b0));
                    g <= ext_g or
                         (ext_e and
                         ((a1 and (not b1)) or (e1 and a0 and (not b0))));
                    l <= ext_l or
                         (ext_e and
                         ((b1 and (not a1)) or (e1 and b0 and (not a0))));
        end if;
        end process;
end logic;