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By: a guest on Jan 7th, 2013  |  syntax: VeriLog  |  size: 2.89 KB  |  hits: 37  |  expires: Never
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  1. module keyboardInput_test(
  2. input ps2_clk,                  // PS/2 clock, ~12kHz
  3. input ps2_in,                   // PS/2 serial data
  4. input G_CLK,                    // global clock, 100kHz
  5. input reset,                    // reset used for clock debounce.
  6. output reg debounced_ps2_clk,   // debounced PS/2 clock.
  7. output reg [0:6] sevenSeg       // 7 segment display.
  8. );
  9.  
  10. /*
  11.  * [0][LSB]xxxxxx[MSB][P][1] <-- Serial data as it is received.
  12.  *
  13.  * [1][P][MSB]xxxxxx[LSB][0] <-- Data after it is stored in the shift-right register.
  14.  *     
  15.  * SCAN_DATA[8:1] signifies the 8-bit scan code for a key that is pressed.
  16.  */
  17.  
  18. reg [10:0] SCAN_DATA;            /* 8-bit scancode from keyboard in addition
  19.                                     to the start, parity, and stop bit.*/                                                                                
  20. reg [10:0] temp_data;            // temporary holder of incoming PS/2 data.
  21. reg [3:0]  counter;              // counts negative clock edges.
  22. reg busy;                        // indicates incoming data from the PS/2 module.
  23.  
  24. /**--Clk debouncing declarations--**/
  25. parameter NDELAY = 524287;
  26. parameter NBITS = 19;
  27. reg [NBITS-1:0] deb_count;
  28. reg xnew;
  29. /**-------------------------------**/
  30.  
  31. always @(posedge G_CLK) begin    // debounce the PS/2 clock.
  32.     if (reset) begin
  33.              xnew <= ps2_clk;
  34.              debounced_ps2_clk <= ps2_clk;
  35.              deb_count <= 0;
  36.     end
  37.     else if (ps2_clk != xnew) begin
  38.              xnew <= ps2_clk;
  39.              deb_count <= 0;
  40.     end
  41.     else if (deb_count == NDELAY)
  42.              debounced_ps2_clk <= xnew;
  43.     else
  44.              deb_count <= deb_count + 1;
  45. end // done with debounce.
  46.  
  47. integer k;
  48. always @(negedge debounced_ps2_clk) begin
  49.     for (k=0; k!=10; k=k+1)     // shift-right register for incoming data.
  50.         temp_data[k] <= temp_data[k+1];
  51.     temp_data[10] <= ps2_in;
  52. end
  53.  
  54. always @(negedge debounced_ps2_clk) begin
  55.     if (counter == 10)          // counts 11 clock edges.
  56.         counter <= 0;
  57.     else
  58.         counter <= counter + 1;
  59. end
  60.  
  61. always @(posedge G_CLK) begin   // busy goes LOW on the 11th clock edge.
  62.     if (counter == 0 && (ps2_clk))
  63.         busy <= 0;
  64.     else
  65.         busy <= 1;
  66. end
  67.  
  68. always@ (negedge busy)         // data transfer is considered to be complete
  69.     SCAN_DATA <= temp_data;    // on the falling edge of the "busy" signal.
  70.          
  71. always@ (SCAN_DATA) begin      // display the numbers pressed on the keyboard.
  72.     case(SCAN_DATA[8:1]) //7'bABCDEFG
  73.         8'h16: sevenSeg <= 7'b0110000; // '1' code
  74.         8'h1E: sevenSeg <= 7'b1101101; // '2'
  75.         8'h26: sevenSeg <= 7'b1111001; // '3'
  76.         8'h25: sevenSeg <= 7'b0110011; // '4'
  77.         8'h2E: sevenSeg <= 7'b1011011; // '5'
  78.         8'h36: sevenSeg <= 7'b1011111; // '6'
  79.         8'h3D: sevenSeg <= 7'b1110000; // '7'
  80.         8'h3E: sevenSeg <= 7'b1111111; // '8'
  81.         8'h46: sevenSeg <= 7'b1111011; // '9'
  82.         8'h45: sevenSeg <= 7'b1111110; // '0'
  83.         8'hF0: sevenSeg <= 7'bx; // "key released" code
  84.         default: sevenSeg <= 7'bx;
  85.     endcase
  86. end
  87. endmodule