library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity L8_nor is
	generic (tp: time := 2 ns);
	port( A : in STD_LOGIC;
		  B : in STD_LOGIC;
		  C : in STD_LOGIC;
		  Y : out STD_LOGIC );
end L8_nor;

architecture Opis_L8_nor of L8_nor is
begin
	 Y <= A nor B nor C after tp;
end Opis_L8_nor;

-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity L8_nand is
	generic (tp: time := 2 ns);
	port( A : in STD_LOGIC;
		  B : in STD_LOGIC;
		  C : in STD_LOGIC;
		  Y : out STD_LOGIC);
end L8_nand;

architecture Opis_L8_nand of L8_nand is
begin
	 Y <= A nand B nand C after tp;
end Opis_L8_nand;