module checkfreq(clkin, refclk, freq);
   input refclk;
   input clkin;
   output [13:0] freq;

	reg freq;
	reg [13:0] count;

	always @(posedge refclk)
	begin
		if (clkin)
		begin
			count = count + 1'd1;
		end
		else
		begin
			freq = (50000/count);    //Clock de controle de 50kHz
		end
	end

endmodule