LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

-- Wishbone address decoder

ENTITY wb_dec is PORT (
-- (partial) wishbone interface
    clk:        IN std_logic;
    rst:        IN std_logic;
    wb_adr:     IN std_logic_vector(31 downto 0);
    wb_cyc:     IN std_logic;

    cs_tdm_dsp0:    OUT std_logic;
    cs_tdm_dsp1:    OUT std_logic;
    cs_tdm_pri0:    OUT std_logic;
    cs_tdm_pri1:    OUT std_logic;
    cs_tdm_fourw:   OUT std_logic;
    cs_tdm_fxs: OUT std_logic;
    cs_tdm_fxo: OUT std_logic;
    cs_dsp:     OUT std_logic;
    cs_pri:     OUT std_logic;
    cs_spi:     OUT std_logic;
    cs_i2c:     OUT std_logic;
    cs_ru:      OUT std_logic;
    cs_flash:   OUT std_logic;
    cs_regs:    OUT std_logic;
    cs_avm:     OUT std_logic
    );
END wb_dec;

ARCHITECTURE a of wb_dec IS

-- wishbone peripheral address masks
constant TDM_MASK_BITS: positive    := 5;
constant REG_MASK_BITS: positive    := 8;
constant AVM_MASK_BITS: positive    := 9;
constant PRI_MASK_BITS: positive    := 12;
constant SPI_MASK_BITS: positive    := 12;
constant I2C_MASK_BITS: positive    := 12;
constant RU_MASK_BITS: positive     := 12;
constant DSP_MASK_BITS: positive    := 22;
constant FLASH_MASK_BITS: positive  := 25;

-- bit positions in the cs_array slv
constant CS_TDM0_BIT: natural       := 0;
constant CS_TDM1_BIT: natural       := 1;
constant CS_TDM2_BIT: natural       := 2;
constant CS_TDM3_BIT: natural       := 3;
constant CS_TDM4_BIT: natural       := 4;
constant CS_TDM5_BIT: natural       := 5;
constant CS_TDM6_BIT: natural       := 6;
constant CS_REGS_BIT: natural       := 7;
constant CS_AVM_BIT: natural        := 8;
constant CS_PRI_BIT: natural        := 9;
constant CS_SPI_BIT: natural        := 10;
constant CS_I2C_BIT: natural        := 11;
constant CS_RU_BIT: natural         := 12;
constant CS_DSP_BIT: natural        := 13;
constant CS_FLASH_BIT: natural      := 14;

signal cs_ary: std_logic_vector(14 downto 0);

-- there are a bunch of address areas to decode
-- create a record which defines an area and a chip select bit to manipulate
type decode_entry is record
    base: std_logic_vector(31 downto 0);        -- base address
    mask: positive;                             -- number of don't-care bits
    cs: natural;                                -- which cs_bit in the cs array
end record;

type decode_array is array(natural range <>) of decode_entry;

constant decode_map : decode_array := (
    (x"00000000", TDM_MASK_BITS, CS_TDM0_BIT),      -- TDM0
    (x"00000020", TDM_MASK_BITS, CS_TDM1_BIT),      -- TDM1
    (x"00000040", TDM_MASK_BITS, CS_TDM2_BIT),      -- TDM2
    (x"00000060", TDM_MASK_BITS, CS_TDM3_BIT),      -- TDM3
    (x"00000080", TDM_MASK_BITS, CS_TDM4_BIT),      -- TDM4
    (x"000000a0", TDM_MASK_BITS, CS_TDM5_BIT),      -- TDM5
    (x"000000c0", TDM_MASK_BITS, CS_TDM6_BIT),      -- TDM6
    (x"00000700", REG_MASK_BITS, CS_REGS_BIT),      -- ctm registers
    (x"00000800", AVM_MASK_BITS, CS_AVM_BIT),       -- avalon master
    (x"00002000", PRI_MASK_BITS, CS_PRI_BIT),       -- PRI framers
    (x"00003000", SPI_MASK_BITS, CS_SPI_BIT),       -- SPI master
    (x"00004000", I2C_MASK_BITS, CS_I2C_BIT),       -- I2C master
    (x"00005000", RU_MASK_BITS, CS_RU_BIT),         -- remote update
    (x"00400000", DSP_MASK_BITS, CS_DSP_BIT),       -- DSP
    (x"02000000", FLASH_MASK_BITS, CS_FLASH_BIT)    -- flash
    );

begin

-- combinatorial logic
    cs_tdm_dsp0 <= cs_ary(CS_TDM0_BIT);
    cs_tdm_dsp1 <= cs_ary(CS_TDM1_BIT);
    cs_tdm_pri0 <= cs_ary(CS_TDM2_BIT);
    cs_tdm_pri1 <= cs_ary(CS_TDM3_BIT);
    cs_tdm_fourw <= cs_ary(CS_TDM4_BIT);
    cs_tdm_fxs <= cs_ary(CS_TDM5_BIT);
    cs_tdm_fxo <= cs_ary(CS_TDM6_BIT);
    cs_dsp <= cs_ary(CS_DSP_BIT);
    cs_pri <= cs_ary(CS_PRI_BIT);
    cs_spi <= cs_ary(CS_SPI_BIT);
    cs_i2c <= cs_ary(CS_I2C_BIT);
    cs_ru <= cs_ary(CS_RU_BIT);
    cs_flash <= cs_ary(CS_FLASH_BIT);
    cs_regs <= cs_ary(CS_REGS_BIT);
    cs_avm <= cs_ary(CS_AVM_BIT);


wb_decode: process(wb_cyc, wb_adr)

function make_mask(addr: std_logic_vector; mbits:positive) return std_logic_vector is
    variable m: std_logic_vector(addr'high downto addr'low);
BEGIN
    m := addr;
    m(mbits - 1 downto m'low) := (others => '-');
    return m;
END function make_mask;

begin
    cs_ary <= (OTHERS => '0');
    if wb_cyc = '1' then
        for i in decode_map'range loop
            if std_match(wb_adr, make_mask(decode_map(i).base, decode_map(i).mask)) then
                cs_ary(decode_map(i).cs) <= '1';
        end loop;
    end if;
end process;
END ARCHITECTURE;