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nvprof output for gtx 460

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  1. $ nvprof --query-events
  2. ======== Available Events:
  3.                             Name   Description
  4. Device 0:
  5.         Domain domain_a:
  6.                  sm_cta_launched:  Number of thread blocks launched on a multiprocessor.
  7.  
  8.                l1_local_load_hit:  Number of cache lines that hit in L1 cache for local memory load accesses. In case of perfect coalescing this increments by 1, 2, and 4 for 32, 64 and 128 bit accesses by a warp respectively.
  9.  
  10.               l1_local_load_miss:   Number of cache lines that miss in L1 cache for local memory load accesses. In case of perfect coalescing this increments by 1, 2, and 4 for 32, 64 and 128 bit accesses by a warp respectively.
  11.  
  12.               l1_local_store_hit:  Number of cache lines that hit in L1 cache for local memory store accesses. In case of perfect coalescing this increments by 1, 2, and 4 for 32, 64 and 128 bit accesses by a warp respectively.
  13.  
  14.              l1_local_store_miss:  Number of cache lines that miss in L1 cache for local memory store accesses. In case of perfect coalescing this increments by 1, 2, and 4 for 32, 64 and 128 bit accesses by a warp respectively.
  15.  
  16.               l1_global_load_hit:  Number of cache lines that hit in L1 cache for global memory load accesses. In case of perfect coalescing this increments by 1, 2, and 4 for 32, 64 and 128 bit accesses by a warp respectively.
  17.  
  18.              l1_global_load_miss:  Number of cache lines that miss in L1 cache for global memory load accesses. In case of perfect coalescing this increments by 1, 2, and 4 for 32, 64 and 128 bit accesses by a warp respectively.
  19.  
  20. uncached_global_load_transaction:  Number of uncached global load transactions. Increments by 1 per transaction. Transaction can be 32/64/96/128B.
  21.  
  22.         global_store_transaction:  Number of global store transactions. Increments by 1 per transaction. Transaction can be 32/64/96/128B.
  23.  
  24.          l1_shared_bank_conflict:  Number of shared bank conflicts caused due to addresses for two or more shared memory requests fall in the same memory bank. Increments by N-1 and 2*(N-1) for a N-way conflict for 32 bit and 64bit shared memory accesses respectively.
  25.  
  26.        tex0_cache_sector_queries:  Number of texture cache requests. This increments by 1 for each 32-byte access.
  27.  
  28.         tex0_cache_sector_misses:  Number of texture cache misses. This increments by 1 for each 32-byte access.
  29.  
  30.        tex1_cache_sector_queries:  Number of texture cache 1 requests. This increments by 1 for each 32-byte access.
  31.  
  32.         tex1_cache_sector_misses:  Number of texture cache 1 misses. This increments by 1 for each 32-byte access.
  33.  
  34.         Domain domain_b:                                                                                                                                                                                          
  35.            fb_subp0_read_sectors:  Number of DRAM read requests to sub partition 0, increments by 1 for 32 byte access.                                                                                            
  36.                                                                                                                                                                                                                    
  37.            fb_subp1_read_sectors:  Number of DRAM read requests to sub partition 1, increments by 1 for 32 byte access.                                                                                            
  38.                                                                                                                                                                                                                    
  39.           fb_subp0_write_sectors:  Number of DRAM write requests to sub partition 0, increments by 1 for 32 byte access.                                                                                          
  40.                                                                                                                                                                                                                    
  41.           fb_subp1_write_sectors:  Number of DRAM write requests to sub partition 1, increments by 1 for 32 byte access.                                                                                          
  42.                                                                                                                                                                                                                    
  43.     l2_subp0_write_sector_misses:  Number of write misses in slice 0 of L2 cache. This increments by 1 for each 32-byte access.                                                                                    
  44.                                                                                                                                                                                                                    
  45.     l2_subp1_write_sector_misses:  Number of write misses in slice 1 of L2 cache. This increments by 1 for each 32-byte access.                                                                                    
  46.                                                                                                                                                                                                                    
  47.      l2_subp0_read_sector_misses:  Number of read misses in slice 0 of L2 cache. This increments by 1 for each 32-byte access.                                                                                    
  48.  
  49.      l2_subp1_read_sector_misses:  Number of read misses in slice 1 of L2 cache. This increments by 1 for each 32-byte access.
  50.  
  51.    l2_subp0_write_sector_queries:  Number of write requests from L1 to slice 0 of L2 cache. This increments by 1 for each 32-byte access.
  52.  
  53.    l2_subp1_write_sector_queries:  Number of write requests from L1 to slice 1 of L2 cache. This increments by 1 for each 32-byte access.
  54.  
  55.     l2_subp0_read_sector_queries:  Number of read requests from L1 to slice 0 of L2 cache. This increments by 1 for each 32-byte access.
  56.  
  57.     l2_subp1_read_sector_queries:  Number of read requests from L1 to slice 1 of L2 cache. This increments by 1 for each 32-byte access.
  58.  
  59. l2_subp0_read_tex_sector_queries:  Number of read requests from Texture cache to slice 0 of L2 cache. This increments by 1 for each 32-byte access.
  60.  
  61. l2_subp1_read_tex_sector_queries:  Number of read requests from Texture cache to slice 1 of L2 cache. This increments by 1 for each 32-byte access.
  62.  
  63.        l2_subp0_read_hit_sectors:  Number of read requests from L1 that hit in slice 0 of L2 cache. This increments by 1 for each 32-byte access.
  64.  
  65.        l2_subp1_read_hit_sectors:  Number of read requests from L1 that hit in slice 1 of L2 cache. This increments by 1 for each 32-byte access.
  66.  
  67.    l2_subp0_read_tex_hit_sectors:  Number of read requests from Texture cache that hit in slice 0 of L2 cache. This increments by 1 for each 32-byte access.
  68.  
  69.    l2_subp1_read_tex_hit_sectors:  Number of read requests from Texture cache that hit in slice 1 of L2 cache. This increments by 1 for each 32-byte access.
  70.  
  71. l2_subp0_read_sysmem_sector_queries:  Number of system memory read requests to slice 0 of L2 cache. This increments by 1 for each 32-byte access.
  72.  
  73. l2_subp1_read_sysmem_sector_queries:  Number of system memory read requests to slice 1 of L2 cache. This increments by 1 for each 32-byte access.
  74.  
  75. l2_subp0_write_sysmem_sector_queries:  Number of system memory write requests to slice 0 of L2 cache. This increments by 1 for each 32-byte access.
  76.  
  77. l2_subp1_write_sysmem_sector_queries:  Number of system memory write requests to slice 1 of L2 cache. This increments by 1 for each 32-byte access.
  78.  
  79. l2_subp0_total_read_sector_queries:  Total read requests to slice 0 of L2 cache. This includes requests from  L1, Texture cache, system memory. This increments by 1 for each 32-byte access.
  80.  
  81. l2_subp1_total_read_sector_queries:  Total read requests to slice 1 of L2 cache. This includes requests from  L1, Texture cache, system memory. This increments by 1 for each 32-byte access.
  82.  
  83. l2_subp0_total_write_sector_queries:  Total write requests to slice 0 of L2 cache. This includes requests from  L1, Texture cache, system memory. This increments by 1 for each 32-byte access.
  84.  
  85. l2_subp1_total_write_sector_queries:  Total write requests to slice 1 of L2 cache. This includes requests from  L1, Texture cache, system memory. This increments by 1 for each 32-byte access.
  86.  
  87.         Domain domain_c:
  88.                    gld_inst_8bit:  Total number of 8-bit global load instructions that are executed by all the threads across all thread blocks.
  89.  
  90.                   gld_inst_16bit:  Total number of 16-bit global load instructions that are executed by all the threads across all thread blocks.
  91.  
  92.                   gld_inst_32bit:  Total number of 32-bit global load instructions that are executed by all the threads across all thread blocks.
  93.  
  94.                   gld_inst_64bit:  Total number of 64-bit global load instructions that are executed by all the threads across all thread blocks.
  95.  
  96.                  gld_inst_128bit:  Total number of 128-bit global load instructions that are executed by all the threads across all thread blocks.
  97.  
  98.                    gst_inst_8bit:  Total number of 8-bit global store instructions that are executed by all the threads across all thread blocks.
  99.  
  100.                   gst_inst_16bit:  Total number of 16-bit global store instructions that are executed by all the threads across all thread blocks.
  101.  
  102.                   gst_inst_32bit:  Total number of 32-bit global store instructions that are executed by all the threads across all thread blocks.
  103.  
  104.                   gst_inst_64bit:  Total number of 64-bit global store instructions that are executed by all the threads across all thread blocks.
  105.  
  106.                  gst_inst_128bit:  Total number of 128-bit global store instructions that are executed by all the threads across all thread blocks.
  107.  
  108.         Domain domain_d:
  109.                       local_load:  Number of executed load instructions where state space is specified as local, increments per warp on a multiprocessor.
  110.  
  111.                      local_store:  Number of executed store instructions where state space is specified as local, increments per warp on a multiprocessor.
  112.  
  113.                      gld_request:  Number of executed load instructions where the state space is not specified and hence generic addressing is used, increments per warp on a multiprocessor. It can include the load operations from global,local and share state space.
  114.  
  115.                      gst_request:  Number of executed store instructions where the state space is not specified and hence generic addressing is used, increments per warp on a multiprocessor. It can include the store operations to global,local and share state space.
  116.  
  117.                      shared_load:  Number of executed load instructions where state space is specified as shared, increments per warp on a multiprocessor.
  118.  
  119.                     shared_store:  Number of executed store instructions where state space is specified as shared, increments per warp on a multiprocessor.
  120.  
  121.                           branch:  Number of branch instructions executed per warp on a multiprocessor.
  122.  
  123.                 divergent_branch:  Number of divergent branches within a warp. This counter will be incremented by one if at least one thread in a warp diverges (that is, follows a different execution path) via a conditional branch.
  124.  
  125.                   warps_launched:  Number of warps launched on a multiprocessor.
  126.  
  127.                 threads_launched:  Number of threads launched on a multiprocessor.
  128.  
  129.                   inst_issued1_0:  Number of single instruction issued per cycle in pipeline 0.
  130.  
  131.                   inst_issued2_0:  Number of dual instructions issued per cycle in pipeline 0.
  132.  
  133.                   inst_issued1_1:  Number of single instruction issued per cycle in pipeline 1.
  134.  
  135.                   inst_issued2_1:  Number of dual instructions issued per cycle in pipeline 1.
  136.  
  137.                  prof_trigger_00:  User profiled generic trigger that can be inserted in any place of the code to collect the related information. Increments per warp.
  138.  
  139.                  prof_trigger_01:  User profiled generic trigger that can be inserted in any place of the code to collect the related information. Increments per warp.
  140.  
  141.                  prof_trigger_02:  User profiled generic trigger that can be inserted in any place of the code to collect the related information. Increments per warp.
  142.  
  143.                  prof_trigger_03:  User profiled generic trigger that can be inserted in any place of the code to collect the related information. Increments per warp.
  144.  
  145.                  prof_trigger_04:  User profiled generic trigger that can be inserted in any place of the code to collect the related information. Increments per warp.
  146.  
  147.                  prof_trigger_05:  User profiled generic trigger that can be inserted in any place of the code to collect the related information. Increments per warp.
  148.  
  149.                  prof_trigger_06:  User profiled generic trigger that can be inserted in any place of the code to collect the related information. Increments per warp.
  150.  
  151.                  prof_trigger_07:  User profiled generic trigger that can be inserted in any place of the code to collect the related information. Increments per warp.
  152.  
  153.                    inst_executed:  Number of instructions executed, do not include replays.
  154.  
  155.           thread_inst_executed_0:  Number of instructions executed by all threads, does not include replays. For each instruction it increments by the number of threads in the warp that execute the instruction in pipeline 0.
  156.  
  157.           thread_inst_executed_2:  Number of instructions executed by all threads, does not include replays. For each instruction it increments by the number of threads in the warp that execute the instruction in pipeline 2.
  158.  
  159.           thread_inst_executed_1:  Number of instructions executed by all threads, does not include replays. For each instruction it increments by the number of threads in the warp that execute the instruction in pipeline 1.
  160.  
  161.           thread_inst_executed_3:  Number of instructions executed by all threads, does not include replays. For each instruction it increments by the number of threads in the warp that execute the instruction in pipeline 3.
  162.  
  163.                     active_warps:  Accumulated number of active warps per cycle. For every cycle it increments by the number of active warps in the cycle which can be in the range 0 to 48.
  164.  
  165.                    active_cycles:  Number of cycles a multiprocessor has at least one active warp.
  166.  
  167.                       atom_count:  Number of warps executing atomic reduction operations for thread-to-thread communication. Increments by one if at least one thread in a warp executes the instruction
  168.  
  169.                       gred_count:  Number of warps executing reduction operations on global and shared memory. Increments by one if at least one thread in a warp executes the instruction
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