Reading XDEF placement.
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.219 . Memory (MB): peak = 869.250 ; gain = 0.000
Restoring placement.
Restored 508 out of 508 XDEF sites from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files:
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 32 instances were transformed.
  IOBUF => IOBUF (OBUFT, IBUF): 32 instances

INFO: [Project 1-484] Checkpoint was created with build 353583
open_checkpoint: Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 870.258 ; gain = 685.359
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command write_bitstream
INFO: [Drc 23-27] Running DRC with 2 threads
ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 163 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: FCLK_CLK0.
ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 25 out of 163 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: led_dutycycle_tri_io[31], led_dutycycle_tri_io[30], led_dutycycle_tri_io[29], led_dutycycle_tri_io[28], led_dutycycle_tri_io[27], led_dutycycle_tri_io[26], led_dutycycle_tri_io[25], led_dutycycle_tri_io[24], led_dutycycle_tri_io[23], led_dutycycle_tri_io[22], led_dutycycle_tri_io[21], led_dutycycle_tri_io[20], led_dutycycle_tri_io[19], led_dutycycle_tri_io[18], led_dutycycle_tri_io[17] (the first 15 of 25 listed).
INFO: [Vivado 12-3199] DRC finished with 2 Errors, 131 Warnings, 1 Advisories
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

    while executing
"write_bitstream -force system_wrapper.bit "
INFO: [Common 17-206] Exiting Vivado at Wed Apr 16 14:00:19 2014...