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Jun 20th, 2016
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  1. #define PIO_CONFIG_BASE (0x01c20800)                    // Peripheral Base
  2.  
  3. struct portconfig_t {
  4.     volatile unsigned int CFG0;
  5.     volatile unsigned int CFG1;
  6.     volatile unsigned int CFG2;
  7.     volatile unsigned int CFG3;
  8.     volatile unsigned int DAT;
  9.     volatile unsigned int DRV0;
  10.     volatile unsigned int DRV1;
  11.     volatile unsigned int PUL0;
  12.     volatile unsigned int PUL1;
  13. };
  14.  
  15. struct gpio_peripheral {
  16.     unsigned long addr_p;
  17.     int mem_fd;
  18.     void *map;
  19.     volatile unsigned int *addr;
  20.  
  21.     // Register
  22. //  volatile unsigned int hwreg[];
  23.     struct portconfig_t *PORTA;             // Port A config structure
  24.     struct portconfig_t *PORTB;             // Port B config structure
  25.     struct portconfig_t *PORTC;             // Port C config structure
  26.     struct portconfig_t *PORTD;             // Port D config structure
  27.     struct portconfig_t *PORTE;             // Port E config structure
  28.     struct portconfig_t *PORTF;             // Port F config structure
  29.     struct portconfig_t *PORTG;             // Port G config structure
  30.     struct portconfig_t *PORTH;             // Port H config structure
  31.     struct portconfig_t *PORTI;             // Port I config structure
  32.  
  33.     volatile unsigned int *PIO_INT_CFG0;        // Interrupt Config 0
  34.     volatile unsigned int *PIO_INT_CFG1;        // Interrupt Config 1
  35.     volatile unsigned int *PIO_INT_CFG2;        // Interrupt Config 2
  36.     volatile unsigned int *PIO_INT_CFG3;        // Interrupt Config 3
  37.     volatile unsigned int *PIO_INT_CTL;     // Interrupt Control
  38.     volatile unsigned int *PIO_INT_STA;     // Interrupt Status
  39.     volatile unsigned int *PIO_INT_DEB;     // Interrupt Debounce
  40. };
  41.  
  42. int map_peripheral(unsigned long *addr_p, int *mem_fd, void **map, volatile unsigned int **addr)
  43. {
  44.     if (!(*addr_p)) {
  45.         printf("Called map_peripheral with uninitilized struct.\n");
  46.         return -1;
  47.     }
  48.  
  49.     // Open /dev/mem
  50.     if ((*mem_fd = open("/dev/mem", O_RDWR | O_SYNC)) < 0) {
  51.         printf("Failed to open /dev/mem, try checking permissions.\n");
  52.         return -1;
  53.     }
  54.  
  55.     *map = mmap(
  56.         NULL,
  57.         BLOCK_SIZE,
  58.         PROT_READ | PROT_WRITE,
  59.         MAP_SHARED,
  60.         *mem_fd,      // file descriptor to physical memory virtual file '/dev/mem'
  61.         *addr_p       // address in physical map to be exposed
  62.     );
  63.  
  64.     if (*map == MAP_FAILED) {
  65.         perror("mmap error");
  66.         return -1;
  67.     }
  68.  
  69.     *addr = (volatile unsigned int *)*map;
  70.  
  71.     return 0;
  72. }
  73.  
  74. /// <summary>
  75. /// gpio_init
  76. ///
  77. ///     Initializes the GPIO peripheral
  78. /// </summary>
  79. /// <param name="p">Pointer to peripheral struct.<see cref = "struct gpio_peripheral" / ></param>
  80. /// <returns>0 on success, nonzero on failure</returns>
  81. int gpio_init(struct gpio_peripheral *p)
  82. {
  83.     p->addr_p = PIO_CONFIG_BASE;
  84.  
  85.     if (map_peripheral(&(p->addr_p), &(p->mem_fd), &(p->map), &(p->addr)) < 0) {
  86.         printf("Unable to map peripheral %d\n", errno);
  87.         return -1;
  88.     }
  89.        
  90.  
  91.     p->PORTA = (p->addr + PORT_OFFSET(A));
  92.     p->PORTB = (p->addr + PORT_OFFSET(B));
  93.     p->PORTC = (p->addr + PORT_OFFSET(C));
  94.     p->PORTD = (p->addr + PORT_OFFSET(D));
  95.     p->PORTE = (p->addr + PORT_OFFSET(E));
  96.     p->PORTF = (p->addr + PORT_OFFSET(F));
  97.     p->PORTG = (p->addr + PORT_OFFSET(G));
  98.     p->PORTH = (p->addr + PORT_OFFSET(H));
  99.     p->PORTI = (p->addr + PORT_OFFSET(I));
  100.  
  101.     p->PIO_INT_CFG0 = (p->addr + PIO_INT_CFG_BASE_OFFSET(0));
  102.     p->PIO_INT_CFG1 = (p->addr + PIO_INT_CFG_BASE_OFFSET(1));
  103.     p->PIO_INT_CFG2 = (p->addr + PIO_INT_CFG_BASE_OFFSET(2));
  104.     p->PIO_INT_CFG3 = (p->addr + PIO_INT_CFG_BASE_OFFSET(3));
  105.     p->PIO_INT_CTL = (p->addr + PIO_INT_CTL_BASE_OFFSET);
  106.     p->PIO_INT_STA = (p->addr + PIO_INT_STA_BASE_OFFSET);
  107.     p->PIO_INT_DEB = (p->addr + PIO_INT_DEB_BASE_OFFSET);
  108.  
  109.     return 0;
  110. }
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