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-- Company:
-- Engineer:
--
-- Create Date:    04:06:21 04/21/2015
-- Design Name:
-- Module Name:    first_file - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity first_file is
	Port(
			switches : in  STD_LOGIC_VECTOR (7 downto 0);
			clk : in  STD_LOGIC;
			count : in STD_LOGIC;
			min : in STD_LOGIC;
			sec : in STD_LOGIC
			m1  : out INTEGER RANGE 0 TO 9;
		   m2  : out INTEGER RANGE 0 TO 9;
		   s1  : out INTEGER RANGE 0 TO 9;
		   s2  : out INTEGER RANGE 0 TO 9;
			doted : out STD_LOGIC);
end first_file;

architecture Behavioral of first_file is

signal num1 : integer :=0;
signal num2 : integer :=0;

signal min_out : integer :=0;
signal sec_out : integer :=0;

component conv_bin_to_dec is
   Port ( bin : in  STD_LOGIC_VECTOR (3 downto 0);
           dec : out INTEGER RANGE 0 TO 9));
end component;
component conv_bin_to_dec is
	Port ( bin : in  STD_LOGIC_VECTOR (3 downto 0);
           dec : out INTEGER RANGE 0 TO 9));
end component;


begin
	bin_to_dec : conv_bin_to_dec port map(switches(3 downto 0, num1));
	bin_to_dec2 : conv_bin_to_dec port map(switches(7 downto 4, num2));
	process(clk)
	begin
		if(clk'event)then
			if(count='1') then
				sec_out <= (sec_out + 1) mod 60;
				if(sec_out=0)
					min_out <= min_out + 1;
			else
				if(sec='1' and min='0') then
					sec_out <= num2*10 + num1;
				elsif(sec='0' and min='1') then
					min_out <= num2*10 + num1;
			end if;

			m1= min_out / 10;
			m2= min_out mod 10;
			s1= sec_out / 10;
			s2= min_out mod 10;
		end if;
	end process;
end Behavioral;