entity sdram_controller is
    generic (
        CLK_PERIOD : integer := 10; -- in ns
        INIT_TIME : integer := 150000; -- in ns
        INIT_PCHG : integer := 10; -- num of iterations
        INIT_AREF : integer := 10; -- num of iterations
        AREF_COUNT : integer := 5000; -- in ns
        BANK_WIDTH : integer := 2; -- in bits
        ROW_WIDTH : integer := 12; -- in bits
        COL_WIDTH : integer := 8; -- in bits
        DATA_WIDTH : integer := 16; -- in bits
        ADDR_WIDTH : integer := 22; -- in bits
        BUF_WIDTH : integer := 12; -- in bits

        -- sdram time parameters
        tCK : integer := 10; -- the same as CLK_PERIOD
        tRP : integer := 20; -- idle after precharge
        tRC : integer := 70; -- idle after auto refresh
        tRCD : integer := 20 -- activate to r/w
    );
    port (
        clock : in std_logic;
        reset : in std_logic;

        -- client 0
        clock0 : in std_logic;
        strobe0 : in std_logic;
        wr0 : in std_logic;
        addr0 : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
        nwords0 : in std_logic_vector(BUF_WIDTH - 1 downto 0);
        busy0 : out std_logic;

        buf_clock_0 : out std_logic;
        buf_wr_0 : out std_logic;
        buf_addr_0 : out std_logic_vector(BUF_WIDTH - 1 downto 0);
        buf_data_i_0 : out std_logic_vector(DATA_WIDTH - 1 downto 0);
        buf_data_o_0 : in std_logic_vector(DATA_WIDTH - 1 downto 0);

        -- client 1
        clock1 : in std_logic;
        strobe1 : in std_logic;
        wr1 : in std_logic;
        addr1 : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
        nwords1 : in std_logic_vector(BUF_WIDTH - 1 downto 0);
        busy1 : out std_logic;

        buf_clock_1 : out std_logic;
        buf_wr_1 : out std_logic;
        buf_addr_1 : out std_logic_vector(BUF_WIDTH - 1 downto 0);
        buf_data_i_1 : out std_logic_vector(DATA_WIDTH - 1 downto 0);
        buf_data_o_1 : in std_logic_vector(DATA_WIDTH - 1 downto 0);

        -- client 2
        clock2 : in std_logic;
        strobe2 : in std_logic;
        wr2 : in std_logic;
        addr2 : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
        nwords2 : in std_logic_vector(BUF_WIDTH - 1 downto 0);
        busy2 : out std_logic;

        buf_clock_2 : out std_logic;
        buf_wr_2 : out std_logic;
        buf_addr_2 : out std_logic_vector(BUF_WIDTH - 1 downto 0);
        buf_data_i_2 : out std_logic_vector(DATA_WIDTH - 1 downto 0);
        buf_data_o_2 : in std_logic_vector(DATA_WIDTH - 1 downto 0);


        -- sdram interface
        ram_clock : out std_logic;
        ram_cke : out std_logic;
        ram_ncs : out std_logic;
        ram_nras : out std_logic;
        ram_ncas : out std_logic;
        ram_nwe : out std_logic;
        ram_bs : out std_logic_vector(BANK_WIDTH - 1 downto 0);
        ram_a : out std_logic_vector(ROW_WIDTH - 1 downto 0);
        ram_dqm : out std_logic_vector(DATA_WIDTH / 8 - 1 downto 0);
        ram_dq : inout std_logic_vector(DATA_WIDTH - 1 downto 0)
    );
end sdram_controller;