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-- Company:
-- Engineer:
--
-- Create Date:    10:11:18 11/26/2014
-- Design Name:
-- Module Name:    pierewsze - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pierewsze is
    Port ( Q : out  STD_LOGIC_VECTOR (2 downto 0);
           DIR : in  STD_LOGIC;
           CE : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           Clr : in  STD_LOGIC);
end pierewsze;

architecture Behavioral of pierewsze is
	SIGNAL T: STD_LOGIC_VECTOR(2 downto 0);
	SIGNAL q1: STD_LOGIC_VECTOR(2 downto 0);
	SIGNAL pom: STD_LOGIC_VECTOR(3 downto 0);
begin

	pom <= DIR & q1;

with pom select
		T <= "001" when "1000",
			  "110" when "1001",
			  "010" when "1110",
			  "011" when "1010",
			  "100" when "1011",
			  "101" when "1100",
			  "111" when "1101",
			  "000" when "1111",

			  "111" when "0000",
			  "101" when "0111",
			  "100" when "0101",
			  "011" when "0100",
			  "010" when "0011",
			  "110" when "0010",
			  "001" when "0110",
			  "000" when "0001",
			  "110" when others;

		process( CLK, Clr )
		begin
			if Clr = '1' then
					q1(2) <= '0';
			elsif rising_edge( CLK ) then
				if CE = '1' then
					q1(2) <= T(2);
				end if;
			end if;
		end process;


		process( CLK, Clr )
		begin
			if Clr = '1' then
					q1(1) <= '0';
			elsif rising_edge( CLK ) then
				if CE = '1' then
					q1(1) <= T(1);
				end if;
			end if;
		end process;


		process( CLK, Clr )
		begin
			if Clr = '1' then
					q1(0) <= '0';
			elsif rising_edge( CLK ) then
				if CE = '1' then
					q1(0) <= T(0);
				end if;
			end if;
		end process;

		Q <= q1;

end Behavioral;