type avg_log is array (0 to 31) of std_Logic_vector(19 downto 0);
signal V1 :avg_log :=(others=>others=>'0');

library ieee;
use ieee.std_logic_1164.all;

package p_avg is
    type avg_log is array (0 to 31) of std_Logic_vector(19 downto 0);
end package p_avg;

use work.p_avg.all;
entity my_e is
    port(
      ...
      V1 : out avg_log := (others => (others => '0'));
      ...
    );
end entity;

library ieee;
use ieee.std_logic_1164.all;

package p_avg is
  type avg_log is array (0 to 31) of std_logic_vector(19 downto 0);
end package p_avg;



library ieee;
use ieee.std_logic_1164.all;
library work;
use work.p_avg.all;

entity my_e is
  port(
    v1_o : out avg_log);
end entity;

architecture sim of my_e is
begin
  v1_o <= (others => (others => '0'));
end architecture;



library ieee;
use ieee.std_logic_1164.all;
library work;
use work.p_avg.all;

entity tb is
end entity;

architecture sim of tb is
  signal v1 : avg_log;
begin

  my_e_1 : entity work.my_e
    port map(
      v1_o => v1);

end architecture;