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  1. /*
  2. * (C) Copyright 2006
  3. * Texas Instruments, <www.ti.com>
  4. * Jian Zhang <jzhang@ti.com>
  5. * Richard Woodruff <r-woodruff2@ti.com>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25.  
  26. #include <common.h>
  27. #include <command.h>
  28. #include <part.h>
  29. #include <fat.h>
  30. #include <asm/arch/cpu.h>
  31. #include <asm/arch/bits.h>
  32. #include <asm/arch/mux.h>
  33. #include <asm/arch/gpio.h>
  34. #include <asm/arch/sys_proto.h>
  35. #include <asm/arch/sys_info.h>
  36. #include <asm/arch/clocks.h>
  37. #include <asm/arch/mem.h>
  38.  
  39. /* params for XM */
  40. #define CORE_DPLL_PARAM_M2 0x09
  41. #define CORE_DPLL_PARAM_M 0x360
  42. #define CORE_DPLL_PARAM_N 0xC
  43.  
  44. /* BeagleBoard revisions */
  45. #define REVISION_AXBX 0x7
  46. #define REVISION_CX 0x6
  47. #define REVISION_C4 0x5
  48. #define REVISION_XM 0x0
  49. #define REVISION_XM_C 0x2
  50.  
  51. /* Used to index into DPLL parameter tables */
  52. struct dpll_param {
  53. unsigned int m;
  54. unsigned int n;
  55. unsigned int fsel;
  56. unsigned int m2;
  57. };
  58.  
  59. typedef struct dpll_param dpll_param;
  60.  
  61. /* Following functions are exported from lowlevel_init.S */
  62. extern dpll_param *get_mpu_dpll_param();
  63. extern dpll_param *get_iva_dpll_param();
  64. extern dpll_param *get_core_dpll_param();
  65. extern dpll_param *get_per_dpll_param();
  66.  
  67. #define __raw_readl(a) (*(volatile unsigned int *)(a))
  68. #define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v))
  69. #define __raw_readw(a) (*(volatile unsigned short *)(a))
  70. #define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v))
  71.  
  72. /*******************************************************
  73. * Routine: delay
  74. * Description: spinning delay to use before udelay works
  75. ******************************************************/
  76. static inline void delay(unsigned long loops)
  77. {
  78. __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
  79. "bne 1b":"=r" (loops):"0"(loops));
  80. }
  81.  
  82. void udelay (unsigned long usecs) {
  83. delay(usecs);
  84. }
  85.  
  86. /*****************************************
  87. * Routine: board_init
  88. * Description: Early hardware init.
  89. *****************************************/
  90. int board_init(void)
  91. {
  92. return 0;
  93. }
  94.  
  95. /*************************************************************
  96. * get_device_type(): tell if GP/HS/EMU/TST
  97. *************************************************************/
  98. u32 get_device_type(void)
  99. {
  100. int mode;
  101. mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
  102. return mode >>= 8;
  103. }
  104.  
  105. /************************************************
  106. * get_sysboot_value(void) - return SYS_BOOT[4:0]
  107. ************************************************/
  108. u32 get_sysboot_value(void)
  109. {
  110. int mode;
  111. mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
  112. return mode;
  113. }
  114.  
  115. /*************************************************************
  116. * Routine: get_mem_type(void) - returns the kind of memory connected
  117. * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
  118. *************************************************************/
  119. u32 get_mem_type(void)
  120. {
  121.  
  122. if (beagle_revision() == REVISION_XM)
  123. return GPMC_NONE;
  124.  
  125. u32 mem_type = get_sysboot_value();
  126. switch (mem_type) {
  127. case 0:
  128. case 2:
  129. case 4:
  130. case 16:
  131. case 22:
  132. return GPMC_ONENAND;
  133.  
  134. case 1:
  135. case 12:
  136. case 15:
  137. case 21:
  138. case 27:
  139. return GPMC_NAND;
  140.  
  141. case 3:
  142. case 6:
  143. return MMC_ONENAND;
  144.  
  145. case 8:
  146. case 11:
  147. case 14:
  148. case 20:
  149. case 26:
  150. return GPMC_MDOC;
  151.  
  152. case 17:
  153. case 18:
  154. case 24:
  155. return MMC_NAND;
  156.  
  157. case 7:
  158. case 10:
  159. case 13:
  160. case 19:
  161. case 25:
  162. default:
  163. return GPMC_NOR;
  164. }
  165. }
  166.  
  167. /******************************************
  168. * get_cpu_rev(void) - extract version info
  169. ******************************************/
  170. u32 get_cpu_rev(void)
  171. {
  172. u32 cpuid = 0;
  173. /* On ES1.0 the IDCODE register is not exposed on L4
  174. * so using CPU ID to differentiate
  175. * between ES2.0 and ES1.0.
  176. */
  177. __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
  178. if ((cpuid & 0xf) == 0x0)
  179. return CPU_3430_ES1;
  180. else
  181. return CPU_3430_ES2;
  182.  
  183. }
  184.  
  185. /******************************************
  186. * cpu_is_3410(void) - returns true for 3410
  187. ******************************************/
  188. u32 cpu_is_3410(void)
  189. {
  190. int status;
  191. if (get_cpu_rev() < CPU_3430_ES2) {
  192. return 0;
  193. } else {
  194. /* read scalability status and return 1 for 3410*/
  195. status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
  196. /* Check whether MPU frequency is set to 266 MHz which
  197. * is nominal for 3410. If yes return true else false
  198. */
  199. if (((status >> 8) & 0x3) == 0x2)
  200. return 1;
  201. else
  202. return 0;
  203. }
  204. }
  205.  
  206. /******************************************
  207. * beagle_identify
  208. * Description: Detect if we are running on a Beagle revision Ax/Bx,
  209. * C1/2/3, C4 or D. This can be done by reading
  210. * the level of GPIO173, GPIO172 and GPIO171. This should
  211. * result in
  212. * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
  213. * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
  214. * GPIO173, GPIO172, GPIO171: 1 0 1 => C4
  215. * GPIO173, GPIO172, GPIO171: 0 0 0 => XM
  216. ******************************************/
  217. int beagle_revision(void)
  218. {
  219. int rev;
  220.  
  221. omap_request_gpio(171);
  222. omap_request_gpio(172);
  223. omap_request_gpio(173);
  224. omap_set_gpio_direction(171, 1);
  225. omap_set_gpio_direction(172, 1);
  226. omap_set_gpio_direction(173, 1);
  227.  
  228. rev = omap_get_gpio_datain(173) << 2 |
  229. omap_get_gpio_datain(172) << 1 |
  230. omap_get_gpio_datain(171);
  231. omap_free_gpio(171);
  232. omap_free_gpio(172);
  233. omap_free_gpio(173);
  234.  
  235. return rev;
  236. }
  237.  
  238. /*****************************************************************
  239. * sr32 - clear & set a value in a bit range for a 32 bit address
  240. *****************************************************************/
  241. void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
  242. {
  243. u32 tmp, msk = 0;
  244. msk = 1 << num_bits;
  245. --msk;
  246. tmp = __raw_readl(addr) & ~(msk << start_bit);
  247. tmp |= value << start_bit;
  248. __raw_writel(tmp, addr);
  249. }
  250.  
  251. /*********************************************************************
  252. * wait_on_value() - common routine to allow waiting for changes in
  253. * volatile regs.
  254. *********************************************************************/
  255. u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
  256. {
  257. u32 i = 0, val;
  258. do {
  259. ++i;
  260. val = __raw_readl(read_addr) & read_bit_mask;
  261. if (val == match_value)
  262. return 1;
  263. if (i == bound)
  264. return 0;
  265. } while (1);
  266. }
  267.  
  268. #ifdef CFG_3430SDRAM_DDR
  269.  
  270. #define MICRON_DDR 0
  271. #define NUMONYX_MCP 1
  272. int identify_xm_ddr()
  273. {
  274. int mfr, id;
  275.  
  276. __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
  277. __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
  278. __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
  279. __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
  280. __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
  281. __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
  282.  
  283. /* Enable the GPMC Mapping */
  284. __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
  285. ((NAND_BASE_ADR>>24) & 0x3F) |
  286. (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
  287. delay(2000);
  288.  
  289. nand_readid(&mfr, &id);
  290. if (mfr == 0)
  291. return MICRON_DDR;
  292. if ((mfr == 0x20) && (id == 0xba))
  293. return NUMONYX_MCP;
  294. }
  295. /*********************************************************************
  296. * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
  297. *********************************************************************/
  298. void config_3430sdram_ddr(void)
  299. {
  300. /* reset sdrc controller */
  301. __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
  302. wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
  303. __raw_writel(0, SDRC_SYSCONFIG);
  304.  
  305. /* setup sdrc to ball mux */
  306. __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
  307.  
  308. switch(beagle_revision()) {
  309. case REVISION_C4:
  310. if (identify_xm_ddr() == NUMONYX_MCP) {
  311. __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */
  312. __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0);
  313. __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1);
  314. __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
  315. __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
  316. __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
  317. __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
  318. __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
  319. __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
  320. } else {
  321. __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
  322. __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
  323. __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
  324. __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
  325. __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
  326. __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
  327. __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
  328. __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
  329. __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
  330. }
  331. break;
  332. case REVISION_XM:
  333. if (identify_xm_ddr() == MICRON_DDR) {
  334. __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
  335. __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
  336. __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1);
  337. __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
  338. __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0);
  339. __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
  340. __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1);
  341. __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
  342. __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
  343. } else {
  344. __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */
  345. __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0);
  346. __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1);
  347. __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
  348. __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
  349. __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
  350. __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
  351. __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
  352. __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
  353. }
  354. break;
  355. default:
  356. __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
  357. __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
  358. __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
  359. __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
  360. __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
  361. __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
  362. __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
  363. __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
  364. __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
  365. }
  366.  
  367. __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
  368.  
  369. /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
  370. __raw_writel(CMD_NOP, SDRC_MANUAL_0);
  371. __raw_writel(CMD_NOP, SDRC_MANUAL_1);
  372.  
  373. delay(5000);
  374.  
  375. __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
  376. __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
  377.  
  378. __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
  379. __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
  380.  
  381. __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
  382. __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
  383.  
  384. /* set mr0 */
  385. __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
  386. __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1);
  387.  
  388. /* set up dll */
  389. __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
  390. delay(0x2000); /* give time to lock */
  391.  
  392. }
  393. #endif /* CFG_3430SDRAM_DDR */
  394.  
  395. /*************************************************************
  396. * get_sys_clk_speed - determine reference oscillator speed
  397. * based on known 32kHz clock and gptimer.
  398. *************************************************************/
  399. u32 get_osc_clk_speed(void)
  400. {
  401. u32 start, cstart, cend, cdiff, cdiv, val;
  402.  
  403. val = __raw_readl(PRM_CLKSRC_CTRL);
  404.  
  405. if (val & SYSCLKDIV_2)
  406. cdiv = 2;
  407. else
  408. cdiv = 1;
  409.  
  410. /* enable timer2 */
  411. val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
  412. __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
  413.  
  414. /* Enable I and F Clocks for GPT1 */
  415. val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
  416. __raw_writel(val, CM_ICLKEN_WKUP);
  417. val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
  418. __raw_writel(val, CM_FCLKEN_WKUP);
  419.  
  420. __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
  421. __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
  422. /* enable 32kHz source */
  423. /* enabled out of reset */
  424. /* determine sys_clk via gauging */
  425.  
  426. start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
  427. while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */
  428. cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
  429. while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */
  430. cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
  431. cdiff = cend - cstart; /* get elapsed ticks */
  432. cdiff *= cdiv;
  433.  
  434. /* based on number of ticks assign speed */
  435. if (cdiff > 19000)
  436. return S38_4M;
  437. else if (cdiff > 15200)
  438. return S26M;
  439. else if (cdiff > 13000)
  440. return S24M;
  441. else if (cdiff > 9000)
  442. return S19_2M;
  443. else if (cdiff > 7600)
  444. return S13M;
  445. else
  446. return S12M;
  447. }
  448.  
  449. /******************************************************************************
  450. * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
  451. * -- input oscillator clock frequency.
  452. *
  453. *****************************************************************************/
  454. void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
  455. {
  456. if (osc_clk == S38_4M)
  457. *sys_clkin_sel = 4;
  458. else if (osc_clk == S26M)
  459. *sys_clkin_sel = 3;
  460. else if (osc_clk == S19_2M)
  461. *sys_clkin_sel = 2;
  462. else if (osc_clk == S13M)
  463. *sys_clkin_sel = 1;
  464. else if (osc_clk == S12M)
  465. *sys_clkin_sel = 0;
  466. }
  467.  
  468. /******************************************************************************
  469. * prcm_init() - inits clocks for PRCM as defined in clocks.h
  470. * -- called from SRAM, or Flash (using temp SRAM stack).
  471. *****************************************************************************/
  472. void prcm_init(void)
  473. {
  474. u32 osc_clk = 0, sys_clkin_sel;
  475. dpll_param *dpll_param_p;
  476. u32 clk_index, sil_index;
  477.  
  478. /* Gauge the input clock speed and find out the sys_clkin_sel
  479. * value corresponding to the input clock.
  480. */
  481. osc_clk = get_osc_clk_speed();
  482. get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
  483.  
  484. sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
  485.  
  486. /* If the input clock is greater than 19.2M always divide/2 */
  487. if (sys_clkin_sel > 2) {
  488. sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */
  489. clk_index = sys_clkin_sel / 2;
  490. } else {
  491. sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */
  492. clk_index = sys_clkin_sel;
  493. }
  494.  
  495. sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
  496.  
  497. /* The DPLL tables are defined according to sysclk value and
  498. * silicon revision. The clk_index value will be used to get
  499. * the values for that input sysclk from the DPLL param table
  500. * and sil_index will get the values for that SysClk for the
  501. * appropriate silicon rev.
  502. */
  503. sil_index = get_cpu_rev() - 1;
  504.  
  505. /* Unlock MPU DPLL (slows things down, and needed later) */
  506. sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
  507. wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
  508.  
  509. /* Getting the base address of Core DPLL param table */
  510. dpll_param_p = (dpll_param *) get_core_dpll_param();
  511. /* Moving it to the right sysclk and ES rev base */
  512. dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
  513. /* CORE DPLL */
  514. /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
  515. sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
  516. wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
  517.  
  518. /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
  519. work. write another value and then default value. */
  520. sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
  521. sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
  522. sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
  523. sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
  524. sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
  525. sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
  526. sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
  527. sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
  528. sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
  529. sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
  530. sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
  531. sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
  532. sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
  533. sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
  534. wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
  535.  
  536. /* Getting the base address to PER DPLL param table */
  537. dpll_param_p = (dpll_param *) get_per_dpll_param();
  538. /* Moving it to the right sysclk base */
  539. dpll_param_p = dpll_param_p + clk_index;
  540. /* PER DPLL */
  541. sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
  542. wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
  543. sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
  544. sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
  545. sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
  546. sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
  547.  
  548. if (beagle_revision() == REVISION_XM) {
  549. sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */
  550. sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */
  551. sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */
  552. } else {
  553. sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
  554. sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
  555. sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
  556. }
  557.  
  558. sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */
  559. sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
  560. wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
  561.  
  562. /* Getting the base address to MPU DPLL param table */
  563. dpll_param_p = (dpll_param *) get_mpu_dpll_param();
  564.  
  565. /* Moving it to the right sysclk and ES rev base */
  566. dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
  567.  
  568. /* MPU DPLL (unlocked already) */
  569. sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
  570. sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
  571. sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
  572. sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
  573. sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
  574. wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
  575.  
  576. /* Getting the base address to IVA DPLL param table */
  577. dpll_param_p = (dpll_param *) get_iva_dpll_param();
  578. /* Moving it to the right sysclk and ES rev base */
  579. dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
  580. /* IVA DPLL (set to 12*20=240MHz) */
  581. sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
  582. wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
  583. sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
  584. sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
  585. sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
  586. sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
  587. sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
  588. wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
  589.  
  590. /* Set up GPTimers to sys_clk source only */
  591. sr32(CM_CLKSEL_PER, 0, 8, 0xff);
  592. sr32(CM_CLKSEL_WKUP, 0, 1, 1);
  593.  
  594. delay(5000);
  595. }
  596.  
  597. /*****************************************
  598. * Routine: secure_unlock
  599. * Description: Setup security registers for access
  600. * (GP Device only)
  601. *****************************************/
  602. void secure_unlock(void)
  603. {
  604. /* Permission values for registers -Full fledged permissions to all */
  605. #define UNLOCK_1 0xFFFFFFFF
  606. #define UNLOCK_2 0x00000000
  607. #define UNLOCK_3 0x0000FFFF
  608. /* Protection Module Register Target APE (PM_RT) */
  609. __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
  610. __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
  611. __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
  612. __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
  613.  
  614. __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
  615. __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
  616. __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
  617.  
  618. __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
  619. __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
  620. __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
  621. __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
  622.  
  623. /* IVA Changes */
  624. __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
  625. __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
  626. __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
  627.  
  628. __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
  629. }
  630.  
  631. /**********************************************************
  632. * Routine: try_unlock_sram()
  633. * Description: If chip is GP type, unlock the SRAM for
  634. * general use.
  635. ***********************************************************/
  636. void try_unlock_memory(void)
  637. {
  638. int mode;
  639.  
  640. /* if GP device unlock device SRAM for general use */
  641. /* secure code breaks for Secure/Emulation device - HS/E/T */
  642. mode = get_device_type();
  643. if (mode == GP_DEVICE)
  644. secure_unlock();
  645. return;
  646. }
  647.  
  648. /**********************************************************
  649. * Routine: s_init
  650. * Description: Does early system init of muxing and clocks.
  651. * - Called at time when only stack is available.
  652. **********************************************************/
  653.  
  654. void s_init(void)
  655. {
  656. watchdog_init();
  657. #ifdef CONFIG_3430_AS_3410
  658. /* setup the scalability control register for
  659. * 3430 to work in 3410 mode
  660. */
  661. __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP);
  662. #endif
  663. try_unlock_memory();
  664. set_muxconf_regs();
  665. delay(100);
  666. per_clocks_enable();
  667. prcm_init();
  668. config_3430sdram_ddr();
  669. }
  670.  
  671. /*******************************************************
  672. * Routine: misc_init_r
  673. * Description: Init ethernet (done here so udelay works)
  674. ********************************************************/
  675. int misc_init_r(void)
  676. {
  677. int rev;
  678.  
  679. rev = beagle_revision();
  680. switch (rev) {
  681. case REVISION_AXBX:
  682. printf("Beagle Rev Ax/Bx\n");
  683. break;
  684. case REVISION_CX:
  685. printf("Beagle Rev C1/C2/C3\n");
  686. break;
  687. case REVISION_C4:
  688. if (identify_xm_ddr() == NUMONYX_MCP)
  689. printf("Beagle Rev C4 from Special Computing\n");
  690. else
  691. printf("Beagle Rev C4\n");
  692. break;
  693. case REVISION_XM:
  694. printf("Beagle xM Rev A\n");
  695. break;
  696.  
  697. case REVISION_XM_C:
  698. printf("Beagle xM Rev A\n");
  699. break;
  700. default:
  701. printf("Beagle unknown sametc 0x%02x\n", rev);
  702. }
  703.  
  704. return 0;
  705. }
  706.  
  707. /******************************************************
  708. * Routine: wait_for_command_complete
  709. * Description: Wait for posting to finish on watchdog
  710. ******************************************************/
  711. void wait_for_command_complete(unsigned int wd_base)
  712. {
  713. int pending = 1;
  714. do {
  715. pending = __raw_readl(wd_base + WWPS);
  716. } while (pending);
  717. }
  718.  
  719. /****************************************
  720. * Routine: watchdog_init
  721. * Description: Shut down watch dogs
  722. *****************************************/
  723. void watchdog_init(void)
  724. {
  725. /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
  726. * either taken care of by ROM (HS/EMU) or not accessible (GP).
  727. * We need to take care of WD2-MPU or take a PRCM reset. WD3
  728. * should not be running and does not generate a PRCM reset.
  729. */
  730. sr32(CM_FCLKEN_WKUP, 5, 1, 1);
  731. sr32(CM_ICLKEN_WKUP, 5, 1, 1);
  732. wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
  733.  
  734. __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
  735. wait_for_command_complete(WD2_BASE);
  736. __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
  737. }
  738.  
  739. /**********************************************
  740. * Routine: dram_init
  741. * Description: sets uboots idea of sdram size
  742. **********************************************/
  743. int dram_init(void)
  744. {
  745. return 0;
  746. }
  747.  
  748. /*****************************************************************
  749. * Routine: peripheral_enable
  750. * Description: Enable the clks & power for perifs (GPT2, UART1,...)
  751. ******************************************************************/
  752. void per_clocks_enable(void)
  753. {
  754. /* Enable GP2 timer. */
  755. sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
  756. sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
  757. sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
  758.  
  759. #ifdef CFG_NS16550
  760. /* UART1 clocks */
  761. sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
  762. sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
  763.  
  764. /* UART 3 Clocks */
  765. sr32(CM_FCLKEN_PER, 11, 1, 0x1);
  766. sr32(CM_ICLKEN_PER, 11, 1, 0x1);
  767.  
  768. #endif
  769.  
  770. #ifdef CONFIG_DRIVER_OMAP34XX_I2C
  771. /* Turn on all 3 I2C clocks */
  772. sr32(CM_FCLKEN1_CORE, 15, 3, 0x7);
  773. sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */
  774. #endif
  775.  
  776. /* Enable the ICLK for 32K Sync Timer as its used in udelay */
  777. sr32(CM_ICLKEN_WKUP, 2, 1, 0x1);
  778.  
  779. sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON);
  780. sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON);
  781. sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON);
  782. sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON);
  783. sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON);
  784. sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON);
  785. sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON);
  786. sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON);
  787. sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON);
  788. sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON);
  789. sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON);
  790. sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON);
  791.  
  792. /* Enable GPIO 5 & GPIO 6 clocks */
  793. sr32(CM_FCLKEN_PER, 17, 2, 0x3);
  794. sr32(CM_ICLKEN_PER, 17, 2, 0x3);
  795.  
  796. delay(1000);
  797. }
  798.  
  799. /* Set MUX for UART, GPMC, SDRC, GPIO */
  800.  
  801. #define MUX_VAL(OFFSET,VALUE)\
  802. __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
  803.  
  804. #define CP(x) (CONTROL_PADCONF_##x)
  805. /*
  806. * IEN - Input Enable
  807. * IDIS - Input Disable
  808. * PTD - Pull type Down
  809. * PTU - Pull type Up
  810. * DIS - Pull type selection is inactive
  811. * EN - Pull type selection is active
  812. * M0 - Mode 0
  813. * The commented string gives the final mux configuration for that pin
  814. */
  815. #define MUX_DEFAULT()\
  816. MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
  817. MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
  818. MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
  819. MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
  820. MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
  821. MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
  822. MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
  823. MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
  824. MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
  825. MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
  826. MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
  827. MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
  828. MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
  829. MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
  830. MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
  831. MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
  832. MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
  833. MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
  834. MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
  835. MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
  836. MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
  837. MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
  838. MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
  839. MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
  840. MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
  841. MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
  842. MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
  843. MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
  844. MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
  845. MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
  846. MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
  847. MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
  848. MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
  849. MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
  850. MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
  851. MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
  852. MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
  853. MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
  854. MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
  855. MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
  856. MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
  857. MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
  858. MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
  859. MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
  860. MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
  861. MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
  862. MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
  863. MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
  864. MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
  865. MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
  866. MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
  867. MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
  868. MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
  869. MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
  870. MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
  871. MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
  872. MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
  873. MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
  874. MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
  875. MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
  876. MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
  877. MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
  878. MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
  879. MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
  880. MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
  881. MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
  882. MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
  883. MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
  884. MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
  885. MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*GPMC_nCS6*/\
  886. MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7*/\
  887. MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
  888. MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
  889. MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
  890. MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
  891. MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
  892. MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPIO_61*/\
  893. MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
  894. MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
  895. MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
  896. MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPIO_64*/\
  897. MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPIO_65*/\
  898. MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
  899. MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
  900. MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
  901. MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
  902. MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
  903. MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
  904. MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
  905. MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
  906. MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
  907. MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
  908. MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
  909. MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
  910. MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
  911. MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
  912. MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
  913. MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
  914. MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\
  915. MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\
  916. MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
  917. MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\
  918. MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
  919. MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
  920. MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
  921. MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
  922. MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
  923. MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
  924. MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
  925. MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
  926. MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
  927. MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
  928. MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
  929. MUX_VAL(CP(McSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
  930. MUX_VAL(CP(McSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
  931. MUX_VAL(CP(McSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\
  932. MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
  933. MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
  934. MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
  935. MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
  936. MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
  937. MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
  938. MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
  939. MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
  940. MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
  941. MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
  942. MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
  943. MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
  944. MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
  945. MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
  946. MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
  947. MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
  948. MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
  949. MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
  950. MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
  951. MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
  952. MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
  953. MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
  954. MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
  955. MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
  956. MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
  957. MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29 */\
  958. MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\
  959. MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/
  960.  
  961. /**********************************************************
  962. * Routine: set_muxconf_regs
  963. * Description: Setting up the configuration Mux registers
  964. * specific to the hardware. Many pins need
  965. * to be moved from protect to primary mode.
  966. *********************************************************/
  967. void set_muxconf_regs(void)
  968. {
  969. MUX_DEFAULT();
  970. }
  971.  
  972. /**********************************************************
  973. * Routine: nand+_init
  974. * Description: Set up nand for nand and jffs2 commands
  975. *********************************************************/
  976.  
  977. int nand_init(void)
  978. {
  979. /* global settings */
  980. __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
  981. __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
  982. __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
  983.  
  984. /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0.
  985. * We configure only GPMC CS0 with required values. Configiring other devices
  986. * at other CS is done in u-boot. So we don't have to bother doing it here.
  987. */
  988. __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
  989. delay(1000);
  990.  
  991. #ifdef CFG_NAND_K9F1G08R0A
  992. if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
  993. __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
  994. __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
  995. __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
  996. __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
  997. __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
  998. __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
  999.  
  1000. /* Enable the GPMC Mapping */
  1001. __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
  1002. ((NAND_BASE_ADR>>24) & 0x3F) |
  1003. (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
  1004. delay(2000);
  1005.  
  1006. if (nand_chip()) {
  1007. #ifdef CFG_PRINTF
  1008. printf("Unsupported Chip!\n");
  1009. #endif
  1010. return 1;
  1011. }
  1012. }
  1013. #endif
  1014.  
  1015. #ifdef CFG_ONENAND
  1016. if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
  1017. __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
  1018. __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
  1019. __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
  1020. __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
  1021. __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
  1022. __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
  1023.  
  1024. /* Enable the GPMC Mapping */
  1025. __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
  1026. ((ONENAND_BASE>>24) & 0x3F) |
  1027. (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
  1028. delay(2000);
  1029.  
  1030. if (onenand_chip()) {
  1031. #ifdef CFG_PRINTF
  1032. printf("OneNAND Unsupported !\n");
  1033. #endif
  1034. return 1;
  1035. }
  1036. }
  1037. #endif
  1038. return 0;
  1039. }
  1040.  
  1041. #define DEBUG_LED1 149 /* gpio */
  1042. #define DEBUG_LED2 150 /* gpio */
  1043.  
  1044. void blinkLEDs()
  1045. {
  1046. void *p;
  1047.  
  1048. /* Alternately turn the LEDs on and off */
  1049. p = (unsigned long *)OMAP34XX_GPIO5_BASE;
  1050. while (1) {
  1051. /* turn LED1 on and LED2 off */
  1052. *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED1 % 32);
  1053. *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED2 % 32);
  1054.  
  1055. /* delay for a while */
  1056. delay(1000);
  1057.  
  1058. /* turn LED1 off and LED2 on */
  1059. *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED1 % 32);
  1060. *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED2 % 32);
  1061.  
  1062. /* delay for a while */
  1063. delay(1000);
  1064. }
  1065. }
  1066.  
  1067. /* optionally do something like blinking LED */
  1068. void board_hang(void)
  1069. {
  1070. while (1)
  1071. blinkLEDs();
  1072. }
  1073.  
  1074. /******************************************************************************
  1075. * Dummy function to handle errors for EABI incompatibility
  1076. *****************************************************************************/
  1077. void raise(void)
  1078. {
  1079. }
  1080.  
  1081. /******************************************************************************
  1082. * Dummy function to handle errors for EABI incompatibility
  1083. *****************************************************************************/
  1084. void abort(void)
  1085. {
  1086. }
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