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Sep 17th, 2014
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VHDL 0.60 KB | None | 0 0
  1.     process (dataRX)   
  2.     variable overflow1, overflow2 : integer;
  3.    
  4.     begin  
  5.         upper <= conv_integer(unsigned(dataRx(7 downto 4)));
  6.         lower <= conv_integer(unsigned(dataRx(3 downto 0)));
  7.    
  8.         if lower > 9 then
  9.             lower <= lower - 10;
  10.             overflow1 := 1;
  11.         else
  12.             overflow1 := 0;
  13.         end if;
  14.        
  15.         if upper > 9 then
  16.             upper <= upper - 10 + overflow1;
  17.             overflow2 := 1;
  18.         else
  19.             upper <= upper + overflow1;
  20.             overflow2 := 0;
  21.         end if;
  22.        
  23.         digit1 <= conv_std_logic_vector(lower, 4);
  24.         digit2 <= conv_std_logic_vector(upper, 4);
  25.         digit3 <= conv_std_logic_vector(overflow2, 4);
  26.     end process;
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