library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity register1 is
    port(
        rst      : in  std_logic;
        end_data : in  std_logic;
        clk      : in  std_logic;
        D        : in  std_logic_vector(7 downto 0);
        Q        : out std_logic_vector(7 downto 0)
    );
end entity register1;

architecture RTL of register1 is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if rst = '1' or end_data = '1' then
                Q <= "UUUUUUUU";
            else
                Q <= D;
            end if;
        end if;
    end process;

end architecture RTL;