-- Akhan Almagambetov
-- Embry-Riddle Aeronautical University
-- D flip-flop (CEC220 Lecture)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dff is
    Port ( d, clk : in STD_LOGIC;
           q : out STD_LOGIC);
end dff;

architecture dff_arch of dff is

begin
    dff_proc : process (clk)
    begin
        if rising_edge(clk) then q <= d;
        end if;
    end process;

end dff_arch;