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-- Company:
-- Engineer:
--
-- Create Date:   03:41:21 05/25/2016
-- Design Name:
-- Module Name:   E:/xilinx/Ny mapp/lab5/DataMemory_tb.vhd
-- Project Name:  lab5
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DataMemory
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY DataMemory_tb IS
END DataMemory_tb;

ARCHITECTURE behavior OF DataMemory_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT DataMemory
    PORT(
         Clk : IN  std_logic;
         Reset : IN  std_logic;
         MemWE : IN  std_logic;
         Address : IN  std_logic_vector(31 downto 0);
         DataIn : IN  std_logic_vector(31 downto 0);
         DataOut : OUT  std_logic_vector(31 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal Clk : std_logic := '0';
   signal Reset : std_logic := '0';
   signal MemWE : std_logic := '0';
   signal Address : std_logic_vector(31 downto 0) := (others => '0');
   signal DataIn : std_logic_vector(31 downto 0) := (others => '0');

    --Outputs
   signal DataOut : std_logic_vector(31 downto 0);

   -- Clock period definitions
   constant Clk_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: DataMemory PORT MAP (
          Clk => Clk,
          Reset => Reset,
          MemWE => MemWE,
          Address => Address,
          DataIn => DataIn,
          DataOut => DataOut
        );

   -- Clock process definitions
   Clk_process :process
   begin
        Clk <= '0';
        wait for Clk_period/2;
        Clk <= '1';
        wait for Clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
            Reset <= '1';
      wait for 2 ns;
            Reset <= '0';
        wait for 50 ns;
            MemWE <= '1';
            Address <= X"00000010";
            DataIn  <= X"00000001";
        wait for 50 ns;
            Address <= X"00000100";
            DataIn  <= X"00000011";
        wait for 50 ns;
            MemWE <= '0';
            Address <= X"01100100";
            DataIn  <= X"00000100";
        wait;


      -- insert stimulus here
   end process;

END;