/*
 * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.

 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.

 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#include <linux/module.h>
#include <linux/io.h>

unsigned int __mxc_cpu_type;
EXPORT_SYMBOL(__mxc_cpu_type);

void mxc_set_cpu_type(unsigned int type)
{
	__mxc_cpu_type = type;
}


#ifdef CONFIG_IPIPE
void ipipe_mach_allow_hwtimer_uaccess(unsigned long aips1, unsigned long aips2)
{
	volatile unsigned long aips_reg;

	if (!cpu_is_mx27()) {
		/*
		 * S/W workaround: Clear the off platform peripheral modules
		 * Supervisor Protect bit for SDMA to access them.
		 */
		__raw_writel(0x0, aips1 + 0x40);
		__raw_writel(0x0, aips1 + 0x44);
		__raw_writel(0x0, aips1 + 0x48);
		__raw_writel(0x0, aips1 + 0x4C);
		aips_reg = __raw_readl(aips1 + 0x50);
		aips_reg &= 0x00FFFFFF;
		__raw_writel(aips_reg, aips1 + 0x50);

		__raw_writel(0x0, aips2 + 0x40);
		__raw_writel(0x0, aips2 + 0x44);
		__raw_writel(0x0, aips2 + 0x48);
		__raw_writel(0x0, aips2 + 0x4C);
		aips_reg = __raw_readl(aips2 + 0x50);
		aips_reg &= 0x00FFFFFF;
		__raw_writel(aips_reg, aips2 + 0x50);
	} else {
		aips_reg = __raw_readl(aips1 + 8);
		aips_reg &= ~(1 << aips2);
		__raw_writel(aips_reg, aips1 + 8);
	}
}
#endif /* CONFIG_IPIPE */