testfulladder

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY testfulladder IS
END testfulladder;

ARCHITECTURE behavior OF testfulladder IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT fulladder
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         cin : IN  std_logic;
         cout : OUT  std_logic;
         s : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';
   signal cin : std_logic := '0';

    --Outputs
   signal cout : std_logic;
   signal s : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: fulladder PORT MAP (
          a => a,
          b => b,
          cin => cin,
          cout => cout,
          s => s
        );


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 100 ns;

      cin <= '0';
        a <= '0';
        b <= '0';

        wait for 100 ns;

      cin <= '0';
        a <= '0';
        b <= '1';

        wait for 100 ns;

      cin <= '0';
        a <= '1';
        b <= '0';

        wait for 100 ns;

      cin <= '0';
        a <= '1';
        b <= '1';

        wait for 100 ns;

      cin <= '1';
        a <= '0';
        b <= '0';

        wait for 100 ns;

      cin <= '1';
        a <= '0';
        b <= '1';

        wait for 100 ns;

      cin <= '1';
        a <= '1';
        b <= '0';

        wait for 100 ns;

      cin <= '1';
        a <= '1';
        b <= '1';

        wait for 100 ns;

      wait;
   end process;

END;