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0001-i915-manual-override-of-lvds-channel-mode.patch

By: a guest on Apr 9th, 2012  |  syntax: Diff  |  size: 4.66 KB  |  hits: 53  |  expires: Never
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  1. commit e3cb536f63bd8e7e0220b801e37434fc13a2df2d
  2. Author: Dan Yang <dsyang92 (at) gmail (dot) com>
  3. Date:   Sat Apr 7 17:58:33 2012 -0400
  4.  
  5.     Implement manual override of LVDS single/dual channel mode (updated)
  6.  
  7. diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
  8. index d04597d..2bee604 100644
  9. --- a/drivers/gpu/drm/i915/i915_drv.c
  10. +++ b/drivers/gpu/drm/i915/i915_drv.c
  11. @@ -74,6 +74,10 @@ MODULE_PARM_DESC(i915_enable_fbc,
  12.                 "Enable frame buffer compression for power savings "
  13.                 "(default: -1 (use per-chip default))");
  14.  
  15. +unsigned int i915_lvds_channels __read_mostly = 0;
  16. +module_param_named(lvds_channels, i915_lvds_channels, int, 0600);
  17. +MODULE_PARM_DESC(lvds_channels, "LVDS channels in use: 0=(default) prove hardware 1=single 2=dual");
  18. +
  19.  unsigned int i915_lvds_downclock __read_mostly = 0;
  20.  module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  21.  MODULE_PARM_DESC(lvds_downclock,
  22. diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
  23. index ae294a0..6b1a198 100644
  24. --- a/drivers/gpu/drm/i915/i915_drv.h
  25. +++ b/drivers/gpu/drm/i915/i915_drv.h
  26. @@ -1010,6 +1010,7 @@ extern int i915_panel_ignore_lid __read_mostly;
  27.  extern unsigned int i915_powersave __read_mostly;
  28.  extern int i915_semaphores __read_mostly;
  29.  extern unsigned int i915_lvds_downclock __read_mostly;
  30. +extern unsigned int i915_lvds_channels __read_mostly;
  31.  extern int i915_panel_use_ssc __read_mostly;
  32.  extern int i915_vbt_sdvo_panel_type __read_mostly;
  33.  extern int i915_enable_rc6 __read_mostly;
  34. diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
  35. index 9ec9755..c3dbb35 100644
  36. --- a/drivers/gpu/drm/i915/intel_display.c
  37. +++ b/drivers/gpu/drm/i915/intel_display.c
  38. @@ -356,6 +356,19 @@ static const intel_limit_t intel_limits_ironlake_display_port = {
  39.         .find_pll = intel_find_pll_ironlake_dp,
  40.  };
  41.  
  42. +static int intel_is_dual_channel_mode(struct drm_crtc *crtc)
  43. +{
  44. +       struct drm_device *dev = crtc->dev;
  45. +       struct drm_i915_private *dev_priv = dev->dev_private;
  46. +       if(i915_lvds_channels) {
  47. +               /* user specified desired channel mode */
  48. +               return (i915_lvds_channels == 2);
  49. +       }
  50. +
  51. +       /* User did not specify mode so probe hardware */
  52. +       return ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP);
  53. +}
  54. +
  55.  static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  56.                                                 int refclk)
  57.  {
  58. @@ -364,8 +377,7 @@ static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  59.         const intel_limit_t *limit;
  60.  
  61.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  62. -               if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
  63. -                   LVDS_CLKB_POWER_UP) {
  64. +               if (intel_is_dual_channel_mode(crtc)) {
  65.                         /* LVDS dual channel */
  66.                         if (refclk == 100000)
  67.                                 limit = &intel_limits_ironlake_dual_lvds_100m;
  68. @@ -388,18 +400,16 @@ static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  69.  
  70.  static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  71.  {
  72. -       struct drm_device *dev = crtc->dev;
  73. -       struct drm_i915_private *dev_priv = dev->dev_private;
  74.         const intel_limit_t *limit;
  75.  
  76.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  77. -               if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  78. -                   LVDS_CLKB_POWER_UP)
  79. +               if (intel_is_dual_channel_mode(crtc)) {
  80.                         /* LVDS with dual channel */
  81.                         limit = &intel_limits_g4x_dual_channel_lvds;
  82. -               else
  83. -                       /* LVDS with dual channel */
  84. +               } else {
  85. +                       /* LVDS with single channel */
  86.                         limit = &intel_limits_g4x_single_channel_lvds;
  87. +               }
  88.         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  89.                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  90.                 limit = &intel_limits_g4x_hdmi;
  91. @@ -531,8 +541,7 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  92.                  * reliably set up different single/dual channel state, if we
  93.                  * even can.
  94.                  */
  95. -               if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  96. -                   LVDS_CLKB_POWER_UP)
  97. +               if (intel_is_dual_channel_mode(crtc))
  98.                         clock.p2 = limit->p2.p2_fast;
  99.                 else
  100.                         clock.p2 = limit->p2.p2_slow;
  101. @@ -581,7 +590,6 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  102.                         int target, int refclk, intel_clock_t *best_clock)
  103.  {
  104.         struct drm_device *dev = crtc->dev;
  105. -       struct drm_i915_private *dev_priv = dev->dev_private;
  106.         intel_clock_t clock;
  107.         int max_n;
  108.         bool found;
  109. @@ -596,8 +604,7 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  110.                         lvds_reg = PCH_LVDS;
  111.                 else
  112.                         lvds_reg = LVDS;
  113. -               if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
  114. -                   LVDS_CLKB_POWER_UP)
  115. +               if (intel_is_dual_channel_mode(crtc))
  116.                         clock.p2 = limit->p2.p2_fast;
  117.                 else
  118.                         clock.p2 = limit->p2.p2_slow;
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