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       / /  (_) /____ | |/_/
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   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Jan  7 2022 00:35:02
 BIOS CRC passed (d026c7c5)

 Migen git sha1: ac70301
 LiteX git sha1: ba792249

--=============== SoC ==================--
CPU:		VexRiscv SMP-LINUX @ 125MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		64KiB
SRAM:		8KiB
L2:		0KiB
SDRAM:		1048576KiB 16-bit @ 1000MT/s (CL-8 CWL-6)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write latency calibration:
m0:0 m1:4
Read leveling:
  m0, b00: |00000000000000000000000000000000| delays: -
  m0, b01: |00000000000000000000000000000000| delays: -
  m0, b02: |11111111100000000000000000000000| delays: 04+-04
  m0, b03: |00000000001111111111100000000000| delays: 15+-05
  m0, b04: |00000000000000000000000111111111| delays: 27+-04
  m0, b05: |00000000000000000000000000000000| delays: -
  m0, b06: |00000000000000000000000000000000| delays: -
  m0, b07: |00000000000000000000000000000000| delays: -
  best: m0, b03 delays: 15+-05
  m1, b00: |00000000000000000000000111111111| delays: 27+-04
  m1, b01: |00000000000000000000000000000000| delays: -
  m1, b02: |00000000000000000000000000000000| delays: -
  m1, b03: |00000000000000000000000000000000| delays: -
  m1, b04: |00000000000000000000000000000000| delays: -
  m1, b05: |00000000000000000000000000000000| delays: -
  m1, b06: |11111111110000000000000000000000| delays: 05+-05
  m1, b07: |00000000001111111111110000000000| delays: 16+-06
  best: m1, b07 delays: 16+-06
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
  bus errors:  72/256
  addr errors: 3785/8192
  data errors: 254902/524288
Memtest KO
Memory initialization failed

--============= Console ================--

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