.EQU INPUT_DIV_PORT = 0x99
.EQU OUTPUT_DIV_PORT = 0x33
.EQU INPUT_RC_PORT = 0xA7
.EQU OUTPUT_RC_PORT = 0xB8
.CSEG
.ORG 0x10

main:
      IN r9,INPUT_DIV_PORT
      IN r10,INPUT_RC_PORT

      LSR r9                   ;LSR(logical right shift) twice to divide by four
      CLC                      ;Clear carry flags after each shift
      LSR r9
      CLC
      OUT r9, OUTPUT_DIV_PORT

      EXOR r10,0xFF            ;XOR eight bits and adds one to get opposite sign
      ADD r10, 0x01
      OUT r10, OUTPUT_RC_PORT

      BRN main