library IEEE;
use ieee.std_logic_1164.all;

entity soma is
	generic (
			n: integer := 16
		);
		port (
			a : in std_logic_vector(n-1 downto 0);
			b : in std_logic_vector(n-1 downto 0);
			clk : in  std_logic;
			q : out std_logic_vector (n-1 downto 0)
		);
end soma;

architecture comport of soma is
	begin
		process(a,b)
			variable v : integer;
			begin
				for v in 0 to (n-1) loop
					if (v=0) then
						q(v) <= a(v) xor b(v);
					else
						q(v) <= a(v) xor b(v) xor (a(v-1) and b(v-1));
					end if;
				end loop;
		end process;
end comport;

------------------------------------------------------------------------------------------------

library IEEE;
use ieee.std_logic_1164.all;

entity somador is
	generic (
		gen : integer := 4
	);

	port (
		A : in std_logic_vector (gen-1 downto 0);
		B : in std_logic_vector (gen-1 downto 0);
		C: in std_logic;
		Q : out std_logic_vector (gen-1 downto 0)
	);
end somador;

architecture rtl of somador is
	component soma is
		generic (
			n: integer := 16
		);
		port (
			a : in std_logic_vector(n-1 downto 0);
			b : in std_logic_vector(n-1 downto 0);
			clk : in  std_logic;
			q : out std_logic_vector (n-1 downto 0)
		);
	end component;

begin
r1 : soma
	generic map(
		n => gen
	)

	port map (
		a => A,
		b => B,
		clk => C,
		q => Q
	);
end rtl;