API tools faq
paste
Advertisement
Guest User

Untitled

a guest
Feb 27th, 2014
128
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 136.53 KB | None | 0 0
raw download clone embed print report
  1. =~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2014.02.27 22:22:31 =~=~=~=~=~=~=~=~=~=~=~=
  2.  
  3.  
  4. coreboot-4.0-5394-gba6b07e-dirty Thu Feb 27 22:09:56 CET 2014 starting...
  5. BSP Family_Model: 00610f31
  6. cpu_init_detectedx = 00000000
  7. agesawrapper_amdinitreset
  8. AmdInitReset: Start
  9.  
  10.  
  11. *** !!AGESA cb_AgesaV0.0.0.1 ***
  12.  
  13. FCH Reset Data Block Allocation: [0x0], Ptr = 0x004001E0
  14. Fch OEM config in INIT RESET Done
  15.  
  16. AmdInitReset: Start
  17.  
  18.  
  19. *** !!AGESA cb_AgesaV0.0.0.1 ***
  20.  
  21.  
  22. AmdInitReset: End
  23.  
  24. AllocateExecutionCache: Start
  25. AllocateExecutionCache: End
  26.  
  27. OptUDIMM : 1
  28. OptRDIMM : 0
  29. OptLRDIMM : 0
  30. OptECC : 0
  31. OptCsIntlv : 1
  32. OptDctIntlv : 1
  33. OptNodeIntlv : 0
  34. OptOnlineSpare : 0
  35. OptAddr2CsTranslator : 0
  36. OptMemRestore : 1
  37. OptMultiSocket : 0
  38. OptPstates : 1
  39. OptSRAT : 0
  40. OptSLIT : 0
  41. OptWHEA : 1
  42. OptDMI : 0
  43. OptEarlySamples : 0
  44.  
  45. VrmCurrentLimit : 90000
  46. VrmLowPowerThreshold : 0
  47. VrmSlewRate : (5000)
  48. VrmAdditionalDelay : (0)
  49. VrmHiSpeedEnable : 1
  50. VrmInrushCurrentLimit : 0
  51. VrmSviOcpLevel : 0
  52. NbVrmCurrentLimit : 60000
  53. NbVrmLowPowerThreshold : (0)
  54. NbVrmSlewRate : (5000)
  55. NbVrmAdditionalDelay : (0)
  56. NbVrmHiSpeedEnable : 0
  57. NbVrmInrushCurrentLimit : (0)
  58.  
  59. NbVrmSviOcpLevel : 0
  60. NumIoApics : 3
  61. MemInitPstate : 0
  62. C1eMode : C1eModeDisabled
  63. C1eOpData : 0
  64. C1eOpdata1 : 0
  65. C1eOpdata2 : 0
  66. C1eOpdata3 : 0
  67. CStateMode : CStateModeC6
  68. CStateOpData : 0
  69. CStateIoBaseAddr : 0x1770
  70. CpbMode : CpbModeDisabled
  71. CoreLevelingMode : CORE_LEVEL_LOWEST
  72.  
  73. ControlFlowMode : (Nfcm)
  74. UseHtAssist : (1)
  75. UseAtmMode : (1)
  76. Use32ByteRefresh : (0)
  77. UseVarMctIsocPriority : (0)
  78. PowerPolicy : CFG_PLATFORM_POWER_POLICY_MOD
  79. DeemphasisList : (((void *)0))
  80. PciMmioAddr : (0xF8000000)
  81. PciMmioSize : (64)
  82. PlatformType : AMD_PLATFORM_MOBILE
  83. PstateCapValue : 0
  84.  
  85. MemBusFreqLimit : 933
  86. TimingModeSelect : 0
  87. MemoryClockSelect : 800
  88. MemUnganged : 1
  89. QRCap : 1
  90. QRType : 1
  91. RDimmCap : 0
  92. LRDimmCap : 1
  93. UDimmCap : 1
  94. SODimmCap : 0
  95. DqsTrainingControl : 1
  96. IgnoreSpdChecksum : 0
  97. UseBurstMode : 0
  98. AllMemClkOn : 0
  99.  
  100. PowerDownEn : 1
  101. PowerDownMode : 1
  102. OnlineSpare : 0
  103. AddrParityEn : 0
  104. BankSwizzle : 1
  105. LimitBelow1TB : 1
  106. CsIntlvEn : 1
  107. NodeIntlvEn : 0
  108. DctIntlvEn : 1
  109.  
  110. UmaMode : UMA_SPECIFIED
  111. UmaSize : 0x2000
  112. UmaAbove4G : 0
  113. UmaAlignment : UMA_4MB_ALIGNED
  114. EccEn : 0
  115. EccRedirect : 0
  116. ScrubDramRate : 0
  117. ScrubL2Rate : 0
  118. ScrubL3Rate : 0
  119. ScrubIcRate : 0
  120. ScrubDcRate : 0
  121. EccSyncFlood : 0
  122. EccSymbolSize : 4
  123. HeapDramAddress : 0xB0000
  124. NodeMem1GBAlign : 0
  125.  
  126. S3LateRestore : 1
  127. AcpiPstateIndependent : 0
  128. ApMtrrSettingsList : (&TrinityApMtrrSettingsList)
  129. ProcessorScopeInSb : 0
  130. ProcessorScopeName0 : 'P'
  131. ProcessorScopeName1 : '0'
  132. GnbHdAudio : 1
  133. AbmSupport : 0
  134. DynamicRefreshRate : 0
  135. LcdBackLightControl : 200
  136. Gnb3dStereoPinIndex : 0
  137. TempPcieMmioBaseAddress : 0xD0000000ul
  138.  
  139. CfgGnbIGPUSSID : 0
  140. CfgGnbHDAudioSSID : 0
  141. CfgGnbPcieSSID : 0x12341022ul
  142. CfgIommuSupport : 0
  143. CfgLvdsSpreadSpectrum : 0
  144. CfgLvdsSpreadSpectrumRate : 0
  145. CfgLvdsPowerOnSeqDigonToDe : 0
  146. CfgLvdsPowerOnSeqDeToVaryBl : 0
  147. CfgLvdsPowerOnSeqDeToDigon : 0
  148. CfgLvdsPowerOnSeqVaryBlToDe : 0
  149. CfgLvdsPowerOnSeqOnToOffDelay : 0
  150. CfgLvdsPowerOnSeqVaryBlToBlon : 3
  151. CfgLvdsPowerOnSeqBlonToVaryBl : 3
  152. CfgLvdsMaxPixelClockFreq : 0
  153. CfgLcdBitDepthControlValue : 0
  154. CfgLvds24bbpPanelMode : 0
  155.  
  156. CfgLvdsMiscControl.FpdiMode : 0
  157.  
  158. CfgLvdsMiscControl.DlChSwap : 0
  159.  
  160. CfgLvdsMiscControl.VsyncActiveLow : 0
  161.  
  162. CfgLvdsMiscControl.HsyncActiveLow : 0
  163.  
  164. CfgLvdsMiscControl.BLONActiveLow : 0
  165.  
  166. CfgPcieRefClkSpreadSpectrum : 36
  167.  
  168. CfgExtVref : 0
  169.  
  170. CfgForceTrainMode : FORCE_TRAIN_AUTO
  171.  
  172. CfgGnbRemoteDisplaySupport : CFG_GNB_REMOTE_DISPLAY_CONFIG
  173.  
  174. CfgIvrsExclusionRangeList : (((void *)0))
  175.  
  176. CfgGnbSyncFloodPinAsNmi : 0
  177.  
  178. CfgIgpuEnableDisablePolicy : 0
  179.  
  180. CfgGnbSwTjOffset : 0
  181.  
  182. CfgDisplayMiscControl.VbiosFastBootEn : 0
  183.  
  184. AmdInitEarly: Start 0
  185.  
  186. AmdHtInitialize: Start
  187. AMD Processor at Node 0 has raw CPUID=610F31.
  188. AmdHtInitialize: End
  189. AmdCpuEarly: Start
  190. Perform core init step 0
  191. Perform core init step 1
  192. Perform core init step 2
  193. Node 0 core 1 APIC ID = 0x11
  194. Perform core init step 3
  195. Perform core init step 4
  196. Socket 0 core 1 begin AP tasking engine
  197. Launch socket 0 core 2
  198. Waiting for socket 0 core 2
  199.  
  200. AmdInitReset: Start
  201.  
  202.  
  203. *** !!AGESA cb_AgesaV0.0.0.1 ***
  204.  
  205.  
  206. AmdInitReset: End
  207.  
  208. AllocateExecutionCache: Start
  209. AllocateExecutionCache: End
  210.  
  211. OptUDIMM : 1
  212. OptRDIMM : 0
  213. OptLRDIMM : 0
  214. OptECC : 0
  215. OptCsIntlv : 1
  216. OptDctIntlv : 1
  217. OptNodeIntlv : 0
  218. OptOnlineSpare : 0
  219. OptAddr2CsTranslator : 0
  220. OptMemRestore : 1
  221. OptMultiSocket : 0
  222. OptPstates : 1
  223. OptSRAT : 0
  224. OptSLIT : 0
  225. OptWHEA : 1
  226. OptDMI : 0
  227. OptEarlySamples : 0
  228.  
  229. VrmCurrentLimit : 90000
  230. VrmLowPowerThreshold : 0
  231. VrmSlewRate : (5000)
  232. VrmAdditionalDelay : (0)
  233. VrmHiSpeedEnable : 1
  234. VrmInrushCurrentLimit : 0
  235. VrmSviOcpLevel : 0
  236. NbVrmCurrentLimit : 60000
  237. NbVrmLowPowerThreshold : (0)
  238. NbVrmSlewRate : (5000)
  239. NbVrmAdditionalDelay : (0)
  240. NbVrmHiSpeedEnable : 0
  241. NbVrmInrushCurrentLimit : (0)
  242.  
  243. NbVrmSviOcpLevel : 0
  244. NumIoApics : 3
  245. MemInitPstate : 0
  246. C1eMode : C1eModeDisabled
  247. C1eOpData : 0
  248. C1eOpdata1 : 0
  249. C1eOpdata2 : 0
  250. C1eOpdata3 : 0
  251. CStateMode : CStateModeC6
  252. CStateOpData : 0
  253. CStateIoBaseAddr : 0x1770
  254. CpbMode : CpbModeDisabled
  255. CoreLevelingMode : CORE_LEVEL_LOWEST
  256.  
  257. ControlFlowMode : (Nfcm)
  258. UseHtAssist : (1)
  259. UseAtmMode : (1)
  260. Use32ByteRefresh : (0)
  261. UseVarMctIsocPriority : (0)
  262. PowerPolicy : CFG_PLATFORM_POWER_POLICY_MOD
  263. DeemphasisList : (((void *)0))
  264. PciMmioAddr : (0xF8000000)
  265. PciMmioSize : (64)
  266. PlatformType : AMD_PLATFORM_MOBILE
  267. PstateCapValue : 0
  268.  
  269. MemBusFreqLimit : 933
  270. TimingModeSelect : 0
  271. MemoryClockSelect : 800
  272. MemUnganged : 1
  273. QRCap : 1
  274. QRType : 1
  275. RDimmCap : 0
  276. LRDimmCap : 1
  277. UDimmCap : 1
  278. SODimmCap : 0
  279. DqsTrainingControl : 1
  280. IgnoreSpdChecksum : 0
  281. UseBurstMode : 0
  282. AllMemClkOn : 0
  283.  
  284. PowerDownEn : 1
  285. PowerDownMode : 1
  286. OnlineSpare : 0
  287. AddrParityEn : 0
  288. BankSwizzle : 1
  289. LimitBelow1TB : 1
  290. CsIntlvEn : 1
  291. NodeIntlvEn : 0
  292. DctIntlvEn : 1
  293.  
  294. UmaMode : UMA_SPECIFIED
  295. UmaSize : 0x2000
  296. UmaAbove4G : 0
  297. UmaAlignment : UMA_4MB_ALIGNED
  298. EccEn : 0
  299. EccRedirect : 0
  300. ScrubDramRate : 0
  301. ScrubL2Rate : 0
  302. ScrubL3Rate : 0
  303. ScrubIcRate : 0
  304. ScrubDcRate : 0
  305. EccSyncFlood : 0
  306. EccSymbolSize : 4
  307. HeapDramAddress : 0xB0000
  308. NodeMem1GBAlign : 0
  309.  
  310. S3LateRestore : 1
  311. AcpiPstateIndependent : 0
  312. ApMtrrSettingsList : (&TrinityApMtrrSettingsList)
  313. ProcessorScopeInSb : 0
  314. ProcessorScopeName0 : 'P'
  315. ProcessorScopeName1 : '0'
  316. GnbHdAudio : 1
  317. AbmSupport : 0
  318. DynamicRefreshRate : 0
  319. LcdBackLightControl : 200
  320. Gnb3dStereoPinIndex : 0
  321. TempPcieMmioBaseAddress : 0xD0000000ul
  322.  
  323. CfgGnbIGPUSSID : 0
  324. CfgGnbHDAudioSSID : 0
  325. CfgGnbPcieSSID : 0x12341022ul
  326. CfgIommuSupport : 0
  327. CfgLvdsSpreadSpectrum : 0
  328. CfgLvdsSpreadSpectrumRate : 0
  329. CfgLvdsPowerOnSeqDigonToDe : 0
  330. CfgLvdsPowerOnSeqDeToVaryBl : 0
  331. CfgLvdsPowerOnSeqDeToDigon : 0
  332. CfgLvdsPowerOnSeqVaryBlToDe : 0
  333. CfgLvdsPowerOnSeqOnToOffDelay : 0
  334. CfgLvdsPowerOnSeqVaryBlToBlon : 3
  335. CfgLvdsPowerOnSeqBlonToVaryBl : 3
  336. CfgLvdsMaxPixelClockFreq : 0
  337. CfgLcdBitDepthControlValue : 0
  338. CfgLvds24bbpPanelMode : 0
  339.  
  340. CfgLvdsMiscControl.FpdiMode : 0
  341.  
  342. CfgLvdsMiscControl.DlChSwap : 0
  343.  
  344. CfgLvdsMiscControl.VsyncActiveLow : 0
  345.  
  346. CfgLvdsMiscControl.HsyncActiveLow : 0
  347.  
  348. CfgLvdsMiscControl.BLONActiveLow : 0
  349.  
  350. CfgPcieRefClkSpreadSpectrum : 36
  351.  
  352. CfgExtVref : 0
  353.  
  354. CfgForceTrainMode : FORCE_TRAIN_AUTO
  355.  
  356. CfgGnbRemoteDisplaySupport : CFG_GNB_REMOTE_DISPLAY_CONFIG
  357.  
  358. CfgIvrsExclusionRangeList : (((void *)0))
  359.  
  360. CfgGnbSyncFloodPinAsNmi : 0
  361.  
  362. CfgIgpuEnableDisablePolicy : 0
  363.  
  364. CfgGnbSwTjOffset : 0
  365.  
  366. CfgDisplayMiscControl.VbiosFastBootEn : 0
  367.  
  368. AmdInitEarly: Start 0
  369.  
  370. AmdHtInitialize: Start
  371. AMD Processor at Node 0 has raw CPUID=610F31.
  372. AmdHtInitialize: End
  373. AmdCpuEarly: Start
  374. Perform core init step 0
  375. Perform core init step 1
  376. Perform core init step 2
  377. Node 0 core 2 APIC ID = 0x12
  378. Perform core init step 3
  379. Perform core init step 4
  380. Socket 0 core 2 begin AP tasking engine
  381. Launch socket 0 core 3
  382. Waiting for socket 0 core 3
  383.  
  384. AmdInitReset: Start
  385.  
  386.  
  387. *** !!AGESA cb_AgesaV0.0.0.1 ***
  388.  
  389.  
  390. AmdInitReset: End
  391.  
  392. AllocateExecutionCache: Start
  393. AllocateExecutionCache: End
  394.  
  395. OptUDIMM : 1
  396. OptRDIMM : 0
  397. OptLRDIMM : 0
  398. OptECC : 0
  399. OptCsIntlv : 1
  400. OptDctIntlv : 1
  401. OptNodeIntlv : 0
  402. OptOnlineSpare : 0
  403. OptAddr2CsTranslator : 0
  404. OptMemRestore : 1
  405. OptMultiSocket : 0
  406. OptPstates : 1
  407. OptSRAT : 0
  408. OptSLIT : 0
  409. OptWHEA : 1
  410. OptDMI : 0
  411. OptEarlySamples : 0
  412.  
  413. VrmCurrentLimit : 90000
  414. VrmLowPowerThreshold : 0
  415. VrmSlewRate : (5000)
  416. VrmAdditionalDelay : (0)
  417. VrmHiSpeedEnable : 1
  418. VrmInrushCurrentLimit : 0
  419. VrmSviOcpLevel : 0
  420. NbVrmCurrentLimit : 60000
  421. NbVrmLowPowerThreshold : (0)
  422. NbVrmSlewRate : (5000)
  423. NbVrmAdditionalDelay : (0)
  424. NbVrmHiSpeedEnable : 0
  425. NbVrmInrushCurrentLimit : (0)
  426.  
  427. NbVrmSviOcpLevel : 0
  428. NumIoApics : 3
  429. MemInitPstate : 0
  430. C1eMode : C1eModeDisabled
  431. C1eOpData : 0
  432. C1eOpdata1 : 0
  433. C1eOpdata2 : 0
  434. C1eOpdata3 : 0
  435. CStateMode : CStateModeC6
  436. CStateOpData : 0
  437. CStateIoBaseAddr : 0x1770
  438. CpbMode : CpbModeDisabled
  439. CoreLevelingMode : CORE_LEVEL_LOWEST
  440.  
  441. ControlFlowMode : (Nfcm)
  442. UseHtAssist : (1)
  443. UseAtmMode : (1)
  444. Use32ByteRefresh : (0)
  445. UseVarMctIsocPriority : (0)
  446. PowerPolicy : CFG_PLATFORM_POWER_POLICY_MOD
  447. DeemphasisList : (((void *)0))
  448. PciMmioAddr : (0xF8000000)
  449. PciMmioSize : (64)
  450. PlatformType : AMD_PLATFORM_MOBILE
  451. PstateCapValue : 0
  452.  
  453. MemBusFreqLimit : 933
  454. TimingModeSelect : 0
  455. MemoryClockSelect : 800
  456. MemUnganged : 1
  457. QRCap : 1
  458. QRType : 1
  459. RDimmCap : 0
  460. LRDimmCap : 1
  461. UDimmCap : 1
  462. SODimmCap : 0
  463. DqsTrainingControl : 1
  464. IgnoreSpdChecksum : 0
  465. UseBurstMode : 0
  466. AllMemClkOn : 0
  467.  
  468. PowerDownEn : 1
  469. PowerDownMode : 1
  470. OnlineSpare : 0
  471. AddrParityEn : 0
  472. BankSwizzle : 1
  473. LimitBelow1TB : 1
  474. CsIntlvEn : 1
  475. NodeIntlvEn : 0
  476. DctIntlvEn : 1
  477.  
  478. UmaMode : UMA_SPECIFIED
  479. UmaSize : 0x2000
  480. UmaAbove4G : 0
  481. UmaAlignment : UMA_4MB_ALIGNED
  482. EccEn : 0
  483. EccRedirect : 0
  484. ScrubDramRate : 0
  485. ScrubL2Rate : 0
  486. ScrubL3Rate : 0
  487. ScrubIcRate : 0
  488. ScrubDcRate : 0
  489. EccSyncFlood : 0
  490. EccSymbolSize : 4
  491. HeapDramAddress : 0xB0000
  492. NodeMem1GBAlign : 0
  493.  
  494. S3LateRestore : 1
  495. AcpiPstateIndependent : 0
  496. ApMtrrSettingsList : (&TrinityApMtrrSettingsList)
  497. ProcessorScopeInSb : 0
  498. ProcessorScopeName0 : 'P'
  499. ProcessorScopeName1 : '0'
  500. GnbHdAudio : 1
  501. AbmSupport : 0
  502. DynamicRefreshRate : 0
  503. LcdBackLightControl : 200
  504. Gnb3dStereoPinIndex : 0
  505. TempPcieMmioBaseAddress : 0xD0000000ul
  506.  
  507. CfgGnbIGPUSSID : 0
  508. CfgGnbHDAudioSSID : 0
  509. CfgGnbPcieSSID : 0x12341022ul
  510. CfgIommuSupport : 0
  511. CfgLvdsSpreadSpectrum : 0
  512. CfgLvdsSpreadSpectrumRate : 0
  513. CfgLvdsPowerOnSeqDigonToDe : 0
  514. CfgLvdsPowerOnSeqDeToVaryBl : 0
  515. CfgLvdsPowerOnSeqDeToDigon : 0
  516. CfgLvdsPowerOnSeqVaryBlToDe : 0
  517. CfgLvdsPowerOnSeqOnToOffDelay : 0
  518. CfgLvdsPowerOnSeqVaryBlToBlon : 3
  519. CfgLvdsPowerOnSeqBlonToVaryBl : 3
  520. CfgLvdsMaxPixelClockFreq : 0
  521. CfgLcdBitDepthControlValue : 0
  522. CfgLvds24bbpPanelMode : 0
  523.  
  524. CfgLvdsMiscControl.FpdiMode : 0
  525.  
  526. CfgLvdsMiscControl.DlChSwap : 0
  527.  
  528. CfgLvdsMiscControl.VsyncActiveLow : 0
  529.  
  530. CfgLvdsMiscControl.HsyncActiveLow : 0
  531.  
  532. CfgLvdsMiscControl.BLONActiveLow : 0
  533.  
  534. CfgPcieRefClkSpreadSpectrum : 36
  535.  
  536. CfgExtVref : 0
  537.  
  538. CfgForceTrainMode : FORCE_TRAIN_AUTO
  539.  
  540. CfgGnbRemoteDisplaySupport : CFG_GNB_REMOTE_DISPLAY_CONFIG
  541.  
  542. CfgIvrsExclusionRangeList : (((void *)0))
  543.  
  544. CfgGnbSyncFloodPinAsNmi : 0
  545.  
  546. CfgIgpuEnableDisablePolicy : 0
  547.  
  548. CfgGnbSwTjOffset : 0
  549.  
  550. CfgDisplayMiscControl.VbiosFastBootEn : 0
  551.  
  552. AmdInitEarly: Start 0
  553.  
  554. AmdHtInitialize: Start
  555. AMD Processor at Node 0 has raw CPUID=610F31.
  556. AmdHtInitialize: End
  557. AmdCpuEarly: Start
  558. Perform core init step 0
  559. Perform core init step 1
  560. Perform core init step 2
  561. Node 0 core 3 APIC ID = 0x13
  562. Perform core init step 3
  563. Perform core init step 4
  564. Socket 0 core 3 begin AP tasking engine
  565. Dispatch CPU features before early power mgmt init
  566. Perform PM init step 0
  567. IsWarmReset = 1.
  568. NoResetLimit = 1
  569. NotConflictResetLimit = 1
  570. WarmResetOnly = 0
  571. ColdResetOnly = 0
  572. Perform PM init step 1
  573. IsWarmReset = 1.
  574. NoResetLimit = 0
  575. NotConflictResetLimit = 1
  576. WarmResetOnly = 0
  577. ColdResetOnly = 1
  578. This PM init step was skipped!
  579. Perform PM init step 2
  580. IsWarmReset = 1.
  581. NoResetLimit = 1
  582. NotConflictResetLimit = 1
  583. WarmResetOnly = 0
  584. ColdResetOnly = 0
  585. F15TnNbPstateDis
  586. NB Pstates disabled
  587. F15TnNbPstateDisCore
  588. F15TnNbPstateDisCore
  589. F15TnNbPstateDisCore
  590. F15TnNbPstateDisCore
  591. Perform PM init step 3
  592. IsWarmReset = 1.
  593. NoResetLimit = 0
  594. NotConflictResetLimit = 1
  595. WarmResetOnly = 1
  596. ColdResetOnly = 0
  597. F15TnPmCoreAfterReset
  598. F15TnPmCoreAfterResetPhase1OnCore
  599. F15TnPmCoreAfterResetPhase1OnCore
  600. F15TnPmCoreAfterResetPhase1OnCore
  601. F15TnPmCoreAfterResetPhase1OnCore
  602.  
  603. * BOUNDS_CHK Event: 08040100 Data: A00C, 0, 0, 0
  604.  
  605. F15TnPmCoreAfterResetPhase2OnCore
  606.  
  607. * BOUNDS_CHK Event: 08040100 Data: A00C, 0, 0, 0
  608.  
  609. F15TnPmCoreAfterResetPhase2OnCore
  610.  
  611. * BOUNDS_CHK Event: 08040100 Data: A00C, 0, 0, 0
  612.  
  613. F15TnPmCoreAfterResetPhase2OnCore
  614. F15TnPmCoreAfterResetPhase2OnCore
  615. Perform PM init step 4
  616. IsWarmReset = 1.
  617. NoResetLimit = 0
  618. NotConflictResetLimit = 1
  619. WarmResetOnly = 1
  620. ColdResetOnly = 0
  621. F15TnPmNbAfterReset
  622. F15TnPmNbAfterResetOnCore
  623. TransitionToNbLow
  624. WaitForNbTransitionToComplete
  625. TransitionToNbHigh
  626. WaitForNbTransitionToComplete
  627. Perform PM init step 5
  628. IsWarmReset = 1.
  629. NoResetLimit = 1
  630. NotConflictResetLimit = 1
  631. WarmResetOnly = 0
  632. ColdResetOnly = 0
  633. F15TnGetProcIddMax - P0
  634. F15TnCmnCalculateCurrentInmA - IddValue=B7, IddDiv=1
  635. F15TnCmnGetIddDivisor - IddDiv=1
  636. IddDivisor=100
  637. CurrentInmA=18300
  638. Pstate 0 ProcIddMax 73200 CmpCap 3
  639. Transition all cores to POST P-state
  640. Dispatch CPU features after early power mgmt init
  641. CoreLevelingAtEarly
  642. CoreLevelMode: 0
  643. Socket 0 Module 0 MaxCoreCountOnNode 4 MinCoreCountOnNode 4 TotalEnabledCoresOnNode 4 EnabledComputeUnit 2 MinNumOfComputeUnit 2
  644. IO C-state is enabled
  645. Init IO C-state Base at 0x1770
  646. C6 is enabled
  647. Halting all APs
  648. AmdCpuEarly: End
  649. GnbEarlyInterfaceTN Enter
  650. GnbBapmLhtcInitTN Enter
  651. R WRITE Space TYPE_D0F0xBC Address 0x1F428, Value 0x20000000
  652. R WRITE Space TYPE_D0F0xBC Address 0x1F638, Value 0x0A00
  653. R WRITE Space TYPE_D0F0xBC Address 0x1F628, Value 0x30383
  654. GnbBapmLhtcInitTN Exit
  655. GnbTjOffsetUpdateTN Enter
  656. R WRITE Space TYPE_D0F0xBC Address 0x1F85C, Value 0x2200089
  657. CPU Rev = 200, Skip GnbTjOffsetUpdateTN
  658. GnbSoftwareTjOffsetTN Enter
  659. GnbBapmCalculateCoeffsTN Enter
  660. R WRITE Space TYPE_D0F0xBC Address 0x1F480, Value 0xDA78004A
  661. X: 0xDA78004A
  662. R WRITE Space TYPE_D0F0xBC Address 0x1F484, Value 0x88B2FD1E
  663. Y: 0x88B2FD1E
  664. R WRITE Space TYPE_D0F0xBC Address 0x1F4F8, Value 0xFF4EFC19
  665. X: 0xFF4EFC19
  666. R WRITE Space TYPE_D0F0xBC Address 0x1F4FC, Value 0x88B2FD1E
  667. Y: 0x88B2FD1E
  668. R WRITE Space TYPE_D0F0xBC Address 0x1F570, Value 0xFFFC4599
  669. X: 0xFFFC4599
  670. R WRITE Space TYPE_D0F0xBC Address 0x1F574, Value 0x88B2FD1E
  671. Y: 0x88B2FD1E
  672. R WRITE Space TYPE_D0F0xBC Address 0x1F488, Value 0xFF3D83B3
  673. X: 0xFF3D83B3
  674. R WRITE Space TYPE_D0F0xBC Address 0x1F48C, Value 0x88B2FD1E
  675. Y: 0x88B2FD1E
  676. R WRITE Space TYPE_D0F0xBC Address 0x1F500, Value 0xDBC4B6C5
  677. X: 0xDBC4B6C5
  678. R WRITE Space TYPE_D0F0xBC Address 0x1F504, Value 0x88B2FD1E
  679. Y: 0x88B2FD1E
  680. R WRITE Space TYPE_D0F0xBC Address 0x1F578, Value 0x555DBC
  681. X: 0x00555DBC
  682. R WRITE Space TYPE_D0F0xBC Address 0x1F57C, Value 0x88B2FD1E
  683. Y: 0x88B2FD1E
  684. R WRITE Space TYPE_D0F0xBC Address 0x1F490, Value 0xFFFD1EBF
  685. X: 0xFFFD1EBF
  686. R WRITE Space TYPE_D0F0xBC Address 0x1F494, Value 0x88B2FD1E
  687. Y: 0x88B2FD1E
  688. R WRITE Space TYPE_D0F0xBC Address 0x1F508, Value 0xFFA0739B
  689. X: 0xFFA0739B
  690. R WRITE Space TYPE_D0F0xBC Address 0x1F50C, Value 0x88B2FD1E
  691. Y: 0x88B2FD1E
  692. R WRITE Space TYPE_D0F0xBC Address 0x1F580, Value 0xF66F32C6
  693. X: 0xF66F32C6
  694. R WRITE Space TYPE_D0F0xBC Address 0x1F584, Value 0x88B2FD1E
  695. Y: 0x88B2FD1E
  696. R WRITE Space TYPE_D0F0xBC Address 0x1F498, Value 0x1C456BDF
  697. X: 0x1C456BDF
  698. R WRITE Space TYPE_D0F0xBC Address 0x1F49C, Value 0xF9C049B3
  699. Y: 0xF9C049B3
  700. R WRITE Space TYPE_D0F0xBC Address 0x1F510, Value 0x1B441DE
  701. X: 0x01B441DE
  702. R WRITE Space TYPE_D0F0xBC Address 0x1F514, Value 0xF9C049B3
  703. Y: 0xF9C049B3
  704. R WRITE Space TYPE_D0F0xBC Address 0x1F588, Value 0xFF9C9743
  705. X: 0xFF9C9743
  706. R WRITE Space TYPE_D0F0xBC Address 0x1F58C, Value 0xF9C049B3
  707. Y: 0xF9C049B3
  708. R WRITE Space TYPE_D0F0xBC Address 0x1F4A0, Value 0x1D4DC66
  709. X: 0x01D4DC66
  710. R WRITE Space TYPE_D0F0xBC Address 0x1F4A4, Value 0xF9C049B3
  711. Y: 0xF9C049B3
  712. R WRITE Space TYPE_D0F0xBC Address 0x1F518, Value 0x1A49BC0C
  713. X: 0x1A49BC0C
  714. R WRITE Space TYPE_D0F0xBC Address 0x1F51C, Value 0xF9C049B3
  715. Y: 0xF9C049B3
  716. R WRITE Space TYPE_D0F0xBC Address 0x1F590, Value 0x3FB5C3
  717. X: 0x003FB5C3
  718. R WRITE Space TYPE_D0F0xBC Address 0x1F594, Value 0xF9C049B3
  719. Y: 0xF9C049B3
  720. R WRITE Space TYPE_D0F0xBC Address 0x1F4A8, Value 0xFFAB61C4
  721. X: 0xFFAB61C4
  722. R WRITE Space TYPE_D0F0xBC Address 0x1F4AC, Value 0xF9C049B3
  723. Y: 0xF9C049B3
  724. R WRITE Space TYPE_D0F0xBC Address 0x1F520, Value 0x6368BE
  725. X: 0x006368BE
  726. R WRITE Space TYPE_D0F0xBC Address 0x1F524, Value 0xF9C049B3
  727. Y: 0xF9C049B3
  728. R WRITE Space TYPE_D0F0xBC Address 0x1F598, Value 0x804421F
  729. X: 0x0804421F
  730. R WRITE Space TYPE_D0F0xBC Address 0x1F59C, Value 0xF9C049B3
  731. Y: 0xF9C049B3
  732. R WRITE Space TYPE_D0F0xBC Address 0x1F4B0, Value 0x8EEA6A
  733. X: 0x008EEA6A
  734. R WRITE Space TYPE_D0F0xBC Address 0x1F4B4, Value 0xFFBE7F2B
  735. Y: 0xFFBE7F2B
  736. R WRITE Space TYPE_D0F0xBC Address 0x1F528, Value 0x4A212D
  737. X: 0x004A212D
  738. R WRITE Space TYPE_D0F0xBC Address 0x1F52C, Value 0xFFBE7F2B
  739. Y: 0xFFBE7F2B
  740. R WRITE Space TYPE_D0F0xBC Address 0x1F5A0, Value 0x1A275E
  741. X: 0x001A275E
  742. R WRITE Space TYPE_D0F0xBC Address 0x1F5A4, Value 0xFFBE7F2B
  743. Y: 0xFFBE7F2B
  744. R WRITE Space TYPE_D0F0xBC Address 0x1F4B8, Value 0x4A212D
  745. X: 0x004A212D
  746. R WRITE Space TYPE_D0F0xBC Address 0x1F4BC, Value 0xFFBE7F2B
  747. Y: 0xFFBE7F2B
  748. R WRITE Space TYPE_D0F0xBC Address 0x1F530, Value 0x7A7B71
  749. X: 0x007A7B71
  750. R WRITE Space TYPE_D0F0xBC Address 0x1F534, Value 0xFFBE7F2B
  751. Y: 0xFFBE7F2B
  752. R WRITE Space TYPE_D0F0xBC Address 0x1F5A8, Value 0x38F8DC
  753. X: 0x0038F8DC
  754. R WRITE Space TYPE_D0F0xBC Address 0x1F5AC, Value 0xFFBE7F2B
  755. Y: 0xFFBE7F2B
  756. R WRITE Space TYPE_D0F0xBC Address 0x1F4C0, Value 0x194CC3
  757. X: 0x00194CC3
  758. R WRITE Space TYPE_D0F0xBC Address 0x1F4C4, Value 0xFFBE7F2B
  759. Y: 0xFFBE7F2B
  760. R WRITE Space TYPE_D0F0xBC Address 0x1F538, Value 0x35EF2E
  761. X: 0x0035EF2E
  762. R WRITE Space TYPE_D0F0xBC Address 0x1F53C, Value 0xFFBE7F2B
  763. Y: 0xFFBE7F2B
  764. R WRITE Space TYPE_D0F0xBC Address 0x1F5B0, Value 0x5EE5FD
  765. X: 0x005EE5FD
  766. R WRITE Space TYPE_D0F0xBC Address 0x1F5B4, Value 0xFFBE7F2B
  767. Y: 0xFFBE7F2B
  768. R WRITE Space TYPE_D0F0xBC Address 0x1F4C8, Value 0x527C0
  769. X: 0x000527C0
  770. R WRITE Space TYPE_D0F0xBC Address 0x1F4CC, Value 0xFFFD4DD7
  771. Y: 0xFFFD4DD7
  772. R WRITE Space TYPE_D0F0xBC Address 0x1F540, Value 0x4D17A
  773. X: 0x0004D17A
  774. R WRITE Space TYPE_D0F0xBC Address 0x1F544, Value 0xFFFD4DD7
  775. Y: 0xFFFD4DD7
  776. R WRITE Space TYPE_D0F0xBC Address 0x1F5B8, Value 0x49A5C
  777. X: 0x00049A5C
  778. R WRITE Space TYPE_D0F0xBC Address 0x1F5BC, Value 0xFFFD4DD7
  779. Y: 0xFFFD4DD7
  780. R WRITE Space TYPE_D0F0xBC Address 0x1F4D0, Value 0x4D17A
  781. X: 0x0004D17A
  782. R WRITE Space TYPE_D0F0xBC Address 0x1F4D4, Value 0xFFFD4DD7
  783. Y: 0xFFFD4DD7
  784. R WRITE Space TYPE_D0F0xBC Address 0x1F548, Value 0x4D17A
  785. X: 0x0004D17A
  786. R WRITE Space TYPE_D0F0xBC Address 0x1F54C, Value 0xFFFD4DD7
  787. Y: 0xFFFD4DD7
  788. R WRITE Space TYPE_D0F0xBC Address 0x1F5C0, Value 0x4B5AE
  789. X: 0x0004B5AE
  790. R WRITE Space TYPE_D0F0xBC Address 0x1F5C4, Value 0xFFFD4DD7
  791. Y: 0xFFFD4DD7
  792. R WRITE Space TYPE_D0F0xBC Address 0x1F4D8, Value 0x49A5C
  793. X: 0x00049A5C
  794. R WRITE Space TYPE_D0F0xBC Address 0x1F4DC, Value 0xFFFD4DD7
  795. Y: 0xFFFD4DD7
  796. R WRITE Space TYPE_D0F0xBC Address 0x1F550, Value 0x4B5AE
  797. X: 0x0004B5AE
  798. R WRITE Space TYPE_D0F0xBC Address 0x1F554, Value 0xFFFD4DD7
  799. Y: 0xFFFD4DD7
  800. R WRITE Space TYPE_D0F0xBC Address 0x1F5C8, Value 0x4D17A
  801. X: 0x0004D17A
  802. R WRITE Space TYPE_D0F0xBC Address 0x1F5CC, Value 0xFFFD4DD7
  803. Y: 0xFFFD4DD7
  804. R WRITE Space TYPE_D0F0xBC Address 0x1F4E0, Value 0x013E
  805. X: 0x0000013E
  806. R WRITE Space TYPE_D0F0xBC Address 0x1F4E4, Value 0xFFFFE43B
  807. Y: 0xFFFFE43B
  808. R WRITE Space TYPE_D0F0xBC Address 0x1F558, Value 0x013E
  809. X: 0x0000013E
  810. R WRITE Space TYPE_D0F0xBC Address 0x1F55C, Value 0xFFFFE43B
  811. Y: 0xFFFFE43B
  812. R WRITE Space TYPE_D0F0xBC Address 0x1F5D0, Value 0x012C
  813. X: 0x0000012C
  814. R WRITE Space TYPE_D0F0xBC Address 0x1F5D4, Value 0xFFFFE43B
  815. Y: 0xFFFFE43B
  816. R WRITE Space TYPE_D0F0xBC Address 0x1F4E8, Value 0x013E
  817. X: 0x0000013E
  818. R WRITE Space TYPE_D0F0xBC Address 0x1F4EC, Value 0xFFFFE43B
  819. Y: 0xFFFFE43B
  820. R WRITE Space TYPE_D0F0xBC Address 0x1F560, Value 0x012C
  821. X: 0x0000012C
  822. R WRITE Space TYPE_D0F0xBC Address 0x1F564, Value 0xFFFFE43B
  823. Y: 0xFFFFE43B
  824. R WRITE Space TYPE_D0F0xBC Address 0x1F5D8, Value 0x012C
  825. X: 0x0000012C
  826. R WRITE Space TYPE_D0F0xBC Address 0x1F5DC, Value 0xFFFFE43B
  827. Y: 0xFFFFE43B
  828. R WRITE Space TYPE_D0F0xBC Address 0x1F4F0, Value 0x013E
  829. X: 0x0000013E
  830. R WRITE Space TYPE_D0F0xBC Address 0x1F4F4, Value 0xFFFFE43B
  831. Y: 0xFFFFE43B
  832. R WRITE Space TYPE_D0F0xBC Address 0x1F568, Value 0x012C
  833. X: 0x0000012C
  834. R WRITE Space TYPE_D0F0xBC Address 0x1F56C, Value 0xFFFFE43B
  835. Y: 0xFFFFE43B
  836. R WRITE Space TYPE_D0F0xBC Address 0x1F5E0, Value 0x012C
  837. X: 0x0000012C
  838. R WRITE Space TYPE_D0F0xBC Address 0x1F5E4, Value 0xFFFFE43B
  839. Y: 0xFFFFE43B
  840. GnbBapmCalculateCoeffsTN Exit
  841. R WRITE Space TYPE_D0F0xBC Address 0x1F920, Value 0x29000E
  842. NBP0 10khz 2BF20 (180000)
  843. UnbCac 1798 (6040)
  844. R WRITE Space TYPE_D0F0xBC Address 0x1F91C, Value 0x1798
  845. R WRITE Space TYPE_D0F0xBC Address 0x1F160, Value 0x25040001
  846. R WRITE Space TYPE_GMM Address 0x0898, Value 0x0031
  847. R WRITE Space TYPE_D0F0xBC Address 0x1F464, Value 0x1000000
  848. R WRITE Space TYPE_D0F0xBC Address 0x1F9A0, Value 0x0D65
  849. R WRITE Space TYPE_D0F0xBC Address 0x1F9A4, Value 0x289A
  850. R WRITE Space TYPE_D0F0xBC Address 0x1F9A8, Value 0x289A
  851. R WRITE Space TYPE_D0F0xBC Address 0x1F9AC, Value 0x0000
  852. R WRITE Space TYPE_D0F0xBC Address 0x1F9B0, Value 0x0000
  853. R WRITE Space TYPE_D0F0xBC Address 0x1F9B4, Value 0x0000
  854. R WRITE Space TYPE_D0F0xBC Address 0x1F9B8, Value 0x0000
  855. R WRITE Space TYPE_D0F0xBC Address 0x1F9BC, Value 0x0000
  856. R WRITE Space TYPE_D0F0xBC Address 0x1F9C0, Value 0x0000
  857. R WRITE Space TYPE_D0F0xBC Address 0x1F9C4, Value 0x0000
  858. R WRITE Space TYPE_D0F0xBC Address 0x1F9C8, Value 0x016F
  859. R WRITE Space TYPE_D0F0xBC Address 0x1F9CC, Value 0x0000
  860. R WRITE Space TYPE_D0F0xBC Address 0x1F9D0, Value 0x0000
  861. R WRITE Space TYPE_D0F0xBC Address 0x1F9D4, Value 0x0000
  862. R WRITE Space TYPE_D0F0xBC Address 0x1F9D8, Value 0x0000
  863. R WRITE Space TYPE_D0F0xBC Address 0x1F9DC, Value 0x16A5
  864. R WRITE Space TYPE_D0F0xBC Address 0x1F9E0, Value 0x0592
  865. R WRITE Space TYPE_D0F0xBC Address 0x1F9E4, Value 0x0000
  866. R WRITE Space TYPE_D0F0xBC Address 0x1F9E8, Value 0x0000
  867. R WRITE Space TYPE_D0F0xBC Address 0x1F9EC, Value 0x0E60
  868. R WRITE Space TYPE_D0F0xBC Address 0x1F9F0, Value 0x0000
  869. R WRITE Space TYPE_D0F0xBC Address 0x1F9F4, Value 0x0E60
  870. R WRITE Space TYPE_D0F0xBC Address 0x1F9F8, Value 0x0000
  871. R WRITE Space TYPE_D0F0xBC Address 0x1F9FC, Value 0x0E60
  872. R WRITE Space TYPE_D0F0xBC Address 0x1FA00, Value 0x0000
  873. R WRITE Space TYPE_D0F0xBC Address 0x1FA04, Value 0x0E60
  874. R WRITE Space TYPE_D0F0xBC Address 0x1FA08, Value 0x0000
  875. R WRITE Space TYPE_D0F0xBC Address 0x1FA0C, Value 0x0E60
  876. R WRITE Space TYPE_D0F0xBC Address 0x1FA10, Value 0x0000
  877. R WRITE Space TYPE_D0F0xBC Address 0x1FA14, Value 0x0E60
  878. R WRITE Space TYPE_D0F0xBC Address 0x1FA18, Value 0x0EC9
  879. R WRITE Space TYPE_D0F0xBC Address 0x1FA1C, Value 0x0EC9
  880. R WRITE Space TYPE_D0F0xBC Address 0x1FA20, Value 0x041A
  881. R WRITE Space TYPE_D0F0xBC Address 0x1FA24, Value 0x041A
  882. R WRITE Space TYPE_D0F0xBC Address 0x1FA28, Value 0x0000
  883. R WRITE Space TYPE_D0F0xBC Address 0x1FA2C, Value 0x0000
  884. R WRITE Space TYPE_D0F0xBC Address 0x1FA30, Value 0x0000
  885. R WRITE Space TYPE_D0F0xBC Address 0x1FA34, Value 0x0000
  886. R WRITE Space TYPE_D0F0xBC Address 0x1FA38, Value 0x0000
  887. R WRITE Space TYPE_D0F0xBC Address 0x1FA3C, Value 0x0F15
  888. R WRITE Space TYPE_D0F0xBC Address 0x1FA40, Value 0x0F15
  889. R WRITE Space TYPE_D0F0xBC Address 0x1FA44, Value 0x0F15
  890. R WRITE Space TYPE_D0F0xBC Address 0x1FA48, Value 0x0F15
  891. R WRITE Space TYPE_D0F0xBC Address 0x1FA4C, Value 0x0F15
  892. R WRITE Space TYPE_D0F0xBC Address 0x1FA50, Value 0x0F15
  893. R WRITE Space TYPE_D0F0xBC Address 0x1FA54, Value 0x0079
  894. R WRITE Space TYPE_D0F0xBC Address 0x1FA58, Value 0x0079
  895. R WRITE Space TYPE_D0F0xBC Address 0x1FA5C, Value 0x0079
  896. R WRITE Space TYPE_D0F0xBC Address 0x1FA60, Value 0x0000
  897. R WRITE Space TYPE_D0F0xBC Address 0x1FA64, Value 0x0000
  898. R WRITE Space TYPE_D0F0xBC Address 0x1FA68, Value 0x0000
  899. R WRITE Space TYPE_D0F0xBC Address 0x1FA6C, Value 0x0000
  900. R WRITE Space TYPE_D0F0xBC Address 0x1FA70, Value 0x03F2
  901. R WRITE Space TYPE_D0F0xBC Address 0x1FA74, Value 0x03F2
  902. R WRITE Space TYPE_D0F0xBC Address 0x1FA78, Value 0x0000
  903. R WRITE Space TYPE_D0F0xBC Address 0x1FA7C, Value 0x0000
  904. R WRITE Space TYPE_D0F0xBC Address 0x1FA80, Value 0x0123
  905. R WRITE Space TYPE_D0F0xBC Address 0x1FA84, Value 0x0000
  906. R WRITE Space TYPE_D0F0xBC Address 0x1FA88, Value 0x0000
  907. R WRITE Space TYPE_D0F0xBC Address 0x1FA8C, Value 0x0000
  908. R WRITE Space TYPE_D0F0xBC Address 0x1FA90, Value 0x0123
  909. R WRITE Space TYPE_D0F0xBC Address 0x1FA94, Value 0x0000
  910. R WRITE Space TYPE_D0F0xBC Address 0x1FA98, Value 0x0000
  911. R WRITE Space TYPE_D0F0xBC Address 0x1FA9C, Value 0x0000
  912. R WRITE Space TYPE_D0F0xBC Address 0x1FAA0, Value 0x0000
  913. R WRITE Space TYPE_D0F0xBC Address 0x1FAA4, Value 0x195B
  914. R WRITE Space TYPE_D0F0xBC Address 0x1FAA8, Value 0x0629
  915. R WRITE Space TYPE_D0F0xBC Address 0x1FAAC, Value 0x0000
  916. R WRITE Space TYPE_D0F0xBC Address 0x1FAB0, Value 0x0000
  917. R WRITE Space TYPE_D0F0xBC Address 0x1FAB4, Value 0x195B
  918. R WRITE Space TYPE_D0F0xBC Address 0x1FAB8, Value 0x0629
  919. R WRITE Space TYPE_D0F0xBC Address 0x1FABC, Value 0x0000
  920. R WRITE Space TYPE_D0F0xBC Address 0x1FAC0, Value 0x0000
  921. R WRITE Space TYPE_D0F0xBC Address 0x1FAC4, Value 0x0000
  922. R WRITE Space TYPE_D0F0xBC Address 0x1FAC8, Value 0x0000
  923. R WRITE Space TYPE_D0F0xBC Address 0x1FACC, Value 0x0000
  924. R WRITE Space TYPE_D0F0xBC Address 0x1FAD0, Value 0x0000
  925. R WRITE Space TYPE_D0F0xBC Address 0x1FAD4, Value 0x0000
  926. R WRITE Space TYPE_D0F0xBC Address 0x1FAD8, Value 0x0755
  927. R WRITE Space TYPE_D0F0xBC Address 0x1FADC, Value 0x0000
  928. R WRITE Space TYPE_D0F0xBC Address 0x1FAE0, Value 0x0755
  929. R WRITE Space TYPE_D0F0xBC Address 0x1FAE4, Value 0x0000
  930. R WRITE Space TYPE_D0F0xBC Address 0x1FAE8, Value 0x0755
  931. R WRITE Space TYPE_D0F0xBC Address 0x1FAEC, Value 0x0000
  932. R WRITE Space TYPE_D0F0xBC Address 0x1FAF0, Value 0x0755
  933. R WRITE Space TYPE_D0F0xBC Address 0x1FAF4, Value 0x0000
  934. R WRITE Space TYPE_D0F0xBC Address 0x1FAF8, Value 0x0755
  935. R WRITE Space TYPE_D0F0xBC Address 0x1FAFC, Value 0x0000
  936. R WRITE Space TYPE_D0F0xBC Address 0x1FB00, Value 0x0755
  937. R WRITE Space TYPE_D0F0xBC Address 0x1FB04, Value 0x0000
  938. R WRITE Space TYPE_D0F0xBC Address 0x1FB08, Value 0x088B
  939. R WRITE Space TYPE_D0F0xBC Address 0x1FB0C, Value 0x1206
  940. R WRITE Space TYPE_D0F0xBC Address 0x1FB10, Value 0x0000
  941. R WRITE Space TYPE_D0F0xBC Address 0x1FB14, Value 0x088B
  942. R WRITE Space TYPE_D0F0xBC Address 0x1FB18, Value 0x1206
  943. R WRITE Space TYPE_D0F0xBC Address 0x1FB1C, Value 0x0000
  944. R WRITE Space TYPE_D0F0xBC Address 0x1FB20, Value 0x0000
  945. GnbSmuServiceRequestV4 Enter
  946. Service Request 19
  947. GnbSmuServiceRequestV4 Exit
  948. GnbBapmMeasuredTempTN Enter
  949. R WRITE Space TYPE_D0F0xBC Address 0x1F428, Value 0x20000000
  950. GnbBapmMeasuredTempTN Exit
  951. R WRITE Space TYPE_D0F0xBC Address 0x1F62C, Value 0x17702328
  952. R WRITE Space TYPE_D0F0xBC Address 0x1F840, Value 0x0000
  953. GnbProcessTableExt Enter
  954. Property - 0x00000100
  955. R WRITE Space TYPE_D0F0 Address 0x0004, Value 0x0006
  956. R WRITE Space TYPE_D0F0 Address 0x004C, Value 0x2002
  957. R WRITE Space TYPE_D0F0 Address 0x0084, Value 0x3000018
  958. R WRITE Space TYPE_D0F0x64 Address 0x0046, Value 0x13061
  959. R WRITE Space TYPE_D0F0x98 Address 0x000C, Value 0x40000808
  960. R WRITE Space TYPE_D0F0xBC Address 0x1F468, Value 0x186A0
  961. R WRITE Space TYPE_SMU_MSG Address 0x0014, Value 0x0000
  962. GnbSmuServiceRequestV4 Enter
  963. Service Request 20
  964. GnbSmuServiceRequestV4 Exit
  965. R WRITE Space TYPE_D0F0xBC Address 0x1F460, Value 0x10000
  966. R WRITE Space TYPE_D0F0xBC Address 0x1F384, Value 0x0060
  967. R WRITE Space TYPE_SMU_MSG Address 0x0012, Value 0x0000
  968. GnbSmuServiceRequestV4 Enter
  969. Service Request 18
  970. GnbSmuServiceRequestV4 Exit
  971. R WRITE Space TYPE_D0F0xBC Address 0x1F460, Value 0x11E00
  972. R WRITE Space TYPE_D0F0xBC Address 0x1F388, Value 0x0389
  973. R WRITE Space TYPE_SMU_MSG Address 0x0011, Value 0x0000
  974. GnbSmuServiceRequestV4 Enter
  975. Service Request 17
  976. GnbSmuServiceRequestV4 Exit
  977. R WRITE Space TYPE_D0F0xBC Address 0x1F400, Value 0x70102
  978. R WRITE Space TYPE_D0F0xBC Address 0x1F428, Value 0x20000001
  979. R WRITE Space TYPE_D0F0xBC Address 0x1F428, Value 0x28000001
  980. R WRITE Space TYPE_D0F0xBC Address 0x1F46C, Value 0x1B58
  981. R WRITE Space TYPE_SMU_MSG Address 0x000C, Value 0x0000
  982. GnbSmuServiceRequestV4 Enter
  983. Service Request 12
  984. GnbSmuServiceRequestV4 Exit
  985. R WRITE Space TYPE_D0F0xBC Address 0x1F428, Value 0x28000005
  986. R WRITE Space TYPE_D0F0xBC Address 0x1F638, Value 0x0A01
  987. R WRITE Space TYPE_SMU_MSG Address 0x000E, Value 0x0000
  988. GnbSmuServiceRequestV4 Enter
  989. Service Request 14
  990. GnbSmuServiceRequestV4 Exit
  991. R WRITE Space TYPE_D0F0xBC Address 0x1F428, Value 0x2800000D
  992. R WRITE Space TYPE_D0F0xBC Address 0x1F46C, Value 0x1001B58
  993. R WRITE Space TYPE_SMU_MSG Address 0x000F, Value 0x0000
  994. GnbSmuServiceRequestV4 Enter
  995. Service Request 15
  996. GnbSmuServiceRequestV4 Exit
  997. R WRITE Space TYPE_D0F0xBC Address 0x1F428, Value 0x3800000D
  998. R WRITE Space TYPE_D0F0xBC Address 0x1F428, Value 0x3800000F
  999. R WRITE Space TYPE_D0F0xBC Address 0x1F46C, Value 0x1011B58
  1000. R WRITE Space TYPE_SMU_MSG Address 0x000D, Value 0x0000
  1001. GnbSmuServiceRequestV4 Enter
  1002. Service Request 13
  1003. GnbSmuServiceRequestV4 Exit
  1004. GnbProcessTableExt Exit
  1005. GnbEarlyInterfaceTN Exit [0x0]
  1006. PcieConfigurationMap Enter
  1007. <---------- PCIe User Config Start------------->
  1008. ComplexDescriptor SocketId - 0
  1009. NumberOfEngines - 12
  1010. Engine Type - PCIe Port
  1011. Start Phy Lane - 0
  1012. End Phy Lane - 3
  1013. PortPresent - 1
  1014. ChannelType - 4
  1015. DeviceNumber - 8
  1016. FunctionNumber - 0
  1017. LinkSpeedCapability - 0
  1018. LinkAspm - 0
  1019. LinkHotplug - 0
  1020. ResetId - 0
  1021. SB link - 1
  1022. MiscControls - 0x400708
  1023. Engine Type - PCIe Port
  1024. Start Phy Lane - 8
  1025. End Phy Lane - 23
  1026. PortPresent - 1
  1027. ChannelType - 4
  1028. DeviceNumber - 2
  1029. FunctionNumber - 0
  1030. LinkSpeedCapability - 0
  1031. LinkAspm - 0
  1032. LinkHotplug - 0
  1033. ResetId - 1
  1034. SB link - 0
  1035. MiscControls - 0x400700
  1036. Engine Type - PCIe Port
  1037. Start Phy Lane - 4
  1038. End Phy Lane - 7
  1039. PortPresent - 1
  1040. ChannelType - 4
  1041. DeviceNumber - 4
  1042. FunctionNumber - 0
  1043. LinkSpeedCapability - 0
  1044. LinkAspm - 0
  1045. LinkHotplug - 0
  1046. ResetId - 1
  1047. SB link - 0
  1048. MiscControls - 0x400700
  1049. Engine Type - Unused
  1050. Start Phy Lane - 0
  1051. End Phy Lane - 3
  1052. Engine Type - DDI Link
  1053. Start Phy Lane - 24
  1054. End Phy Lane - 27
  1055. ConnectorType - 4
  1056. AuxIndex - 0
  1057. HdpIndex - 0
  1058. Engine Type - DDI Link
  1059. Start Phy Lane - 28
  1060. End Phy Lane - 31
  1061. ConnectorType - 7
  1062. AuxIndex - 1
  1063. HdpIndex - 1
  1064. Engine Type - DDI Link
  1065. Start Phy Lane - 32
  1066. End Phy Lane - 35
  1067. ConnectorType - 4
  1068. AuxIndex - 2
  1069. HdpIndex - 2
  1070. Engine Type - Invalid
  1071. Start Phy Lane - 0
  1072. End Phy Lane - 1024
  1073. Engine Type - Invalid
  1074. Start Phy Lane - 65283
  1075. End Phy Lane - 65535
  1076. Engine Type - Unused
  1077. Start Phy Lane - 65535
  1078. End Phy Lane - 255
  1079. Engine Type - Invalid
  1080. Start Phy Lane - 65535
  1081. End Phy Lane - 0
  1082. Engine Type - Invalid
  1083. Start Phy Lane - 255
  1084. End Phy Lane - 65280
  1085. <---------- PCIe User Config End-------------->
  1086. PcieMapTopologyOnComplex Enter
  1087. PcieMapTopologyOnWrapper Enter
  1088. PcieEnginesToWrapper Enter
  1089. PcieEnginesToWrapper Exit [0]
  1090. PcieEnginesToWrapper Enter
  1091. PcieEnginesToWrapper Exit [0]
  1092. PcieMapTopologyOnWrapper Exit [0]
  1093. PcieMapTopologyOnWrapper Enter
  1094. PcieEnginesToWrapper Enter
  1095. PcieEnginesToWrapper Exit [0]
  1096. PcieMapTopologyOnWrapper Exit [0]
  1097. PcieMapTopologyOnWrapper Enter
  1098. PcieEnginesToWrapper Enter
  1099. PcieEnginesToWrapper Exit [0]
  1100. PcieMapTopologyOnWrapper Exit [0]
  1101. PcieMapTopologyOnWrapper Enter
  1102. PcieEnginesToWrapper Enter
  1103. PcieEnginesToWrapper Exit [0]
  1104. PcieMapTopologyOnWrapper Exit [0]
  1105. PcieMapPortPciAddressTN Enter
  1106. R WRITE Space TYPE_D0F0x64 Address 0x0020, Value 0xBA976542
  1107. R WRITE Space TYPE_D0F0x64 Address 0x0020, Value 0xBA976543
  1108. R WRITE Space TYPE_D0F0x64 Address 0x0021, Value 0x32EDC
  1109. R WRITE Space TYPE_D0F0x64 Address 0x0020, Value 0xBA976543
  1110. PcieMapPortPciAddressTN Exit [0x0]
  1111. PcieMapPortPciAddressTN Enter
  1112. R WRITE Space TYPE_D0F0x64 Address 0x0020, Value 0xBA976542
  1113. R WRITE Space TYPE_D0F0x64 Address 0x0020, Value 0xBA976543
  1114. R WRITE Space TYPE_D0F0x64 Address 0x0021, Value 0x32EDC
  1115. R WRITE Space TYPE_D0F0x64 Address 0x0020, Value 0xBA976543
  1116. PcieMapPortPciAddressTN Exit [0x0]
  1117. PcieMapPortPciAddressTN Enter
  1118. PcieMapPortPciAddressTN Exit [0x0]
  1119. PcieMapTopologyOnComplex Exit [0]
  1120. <-------------- PCIe Config Start------------>
  1121. PSPP Policy - Disabled
  1122. GFX Workaround - Disabled
  1123. LinkL0Pooling - 60000us
  1124. LinkGpioResetAssertionTime - 2000us
  1125. LinkReceiverDetectionPooling - 60000us
  1126. Training Algorythm - PcieTrainingStandard
  1127. <---------- Complex Config Start ---------->
  1128. Descriptor Flags - 0xE2000000
  1129. Socket ID - 0
  1130. <---------- Silicon Config Start -------->
  1131. Descriptor Flags - 0xE1000000
  1132. Silicon ID - 0
  1133. Node ID - 0
  1134. Host PCI Address - 0:0:0
  1135. <---------Wrapper - GFX Config -------->
  1136. Start PHY lane - 8
  1137. End PHY lane - 23
  1138. Descriptor Flags - 0x00C00000
  1139. PowerOffUnusedLanes - 1
  1140. PowerOffUnusedPlls - 1
  1141. ClkGating - 1
  1142. LclkGating - 1
  1143. TxclkGatingPllPowerDown - 1
  1144. PllOffInL1 - 1
  1145. <---------Wrapper - GFX Config End----->
  1146. Descriptor Flags - 0x10200000
  1147. Engine Type - PCIe Port
  1148. Start Phy Lane - 8
  1149. End Phy Lane - 23
  1150. Scrath - 1
  1151. Init Status - 0x00000000
  1152. PCIe port configuration:
  1153. Port Training - Enabled
  1154. Start Core Lane - 0
  1155. End Core Lane - 15
  1156. Requested PCI Dev Number - 2
  1157. Requested PCI Func Number - 0
  1158. PCI Address - 0:2:0
  1159. Misc Control - 0x00
  1160. Native PCI Dev Number - 2
  1161. Native PCI Func Number - 0
  1162. Hotplug - Disabled
  1163. ASPM - Disabled
  1164. Speed - 0
  1165. <---------Wrapper - GPPSB Config -------->
  1166. Start PHY lane - 0
  1167. End PHY lane - 7
  1168. Descriptor Flags - 0x00800000
  1169. PowerOffUnusedLanes - 1
  1170. PowerOffUnusedPlls - 1
  1171. ClkGating - 1
  1172. LclkGating - 1
  1173. TxclkGatingPllPowerDown - 1
  1174. PllOffInL1 - 1
  1175. <---------Wrapper - GPPSB Config End----->
  1176. Descriptor Flags - 0x10200000
  1177. Engine Type - PCIe Port
  1178. Start Phy Lane - 4
  1179. End Phy Lane - 7
  1180. Scrath - 2
  1181. Init Status - 0x00000000
  1182. PCIe port configuration:
  1183. Port Training - Enabled
  1184. Start Core Lane - 4
  1185. End Core Lane - 7
  1186. Requested PCI Dev Number - 4
  1187. Requested PCI Func Number - 0
  1188. PCI Address - 0:4:0
  1189. Misc Control - 0x00
  1190. Native PCI Dev Number - 4
  1191. Native PCI Func Number - 0
  1192. Hotplug - Disabled
  1193. ASPM - Disabled
  1194. Speed - 0
  1195. Descriptor Flags - 0x90200000
  1196. Engine Type - PCIe Port
  1197. Start Phy Lane - 0
  1198. End Phy Lane - 3
  1199. Scrath - 0
  1200. Init Status - 0x00000008
  1201. PCIe port configuration:
  1202. Port Training - Enabled
  1203. Start Core Lane - 0
  1204. End Core Lane - 3
  1205. Requested PCI Dev Number - 8
  1206. Requested PCI Func Number - 0
  1207. PCI Address - 0:8:0
  1208. Misc Control - 0x08
  1209. Native PCI Dev Number - 8
  1210. Native PCI Func Number - 0
  1211. Hotplug - Disabled
  1212. ASPM - Disabled
  1213. Speed - 0
  1214. <---------Wrapper - DDI Config -------->
  1215. Start PHY lane - 24
  1216. End PHY lane - 31
  1217. Descriptor Flags - 0x00400000
  1218. PowerOffUnusedLanes - 1
  1219. PowerOffUnusedPlls - 1
  1220. ClkGating - 1
  1221. LclkGating - 1
  1222. TxclkGatingPllPowerDown - 1
  1223. PllOffInL1 - 0
  1224. <---------Wrapper - DDI Config End----->
  1225. Descriptor Flags - 0x10100000
  1226. Engine Type - DDI Link
  1227. Start Phy Lane - 24
  1228. End Phy Lane - 27
  1229. Scrath - 4
  1230. Init Status - 0x00000000
  1231. DDI configuration:
  1232. Connector - HDMI
  1233. Aux - Aux1
  1234. Hdp - Hdp1
  1235. Descriptor Flags - 0x90100000
  1236. Engine Type - DDI Link
  1237. Start Phy Lane - 28
  1238. End Phy Lane - 31
  1239. Scrath - 5
  1240. Init Status - 0x00000000
  1241. DDI configuration:
  1242. Connector - Hudson-2 Nutmeg DP-to-VGA
  1243. Aux - Aux2
  1244. Hdp - Hdp2
  1245. <---------Wrapper - DDI2 Config -------->
  1246. Start PHY lane - 32
  1247. End PHY lane - 38
  1248. Descriptor Flags - 0xE0400000
  1249. PowerOffUnusedLanes - 1
  1250. PowerOffUnusedPlls - 1
  1251. ClkGating - 1
  1252. LclkGating - 1
  1253. TxclkGatingPllPowerDown - 1
  1254. PllOffInL1 - 0
  1255. <---------Wrapper - DDI2 Config End----->
  1256. Descriptor Flags - 0xF0100000
  1257. Engine Type - DDI Link
  1258. Start Phy Lane - 32
  1259. End Phy Lane - 35
  1260. Scrath - 6
  1261. Init Status - 0x00000000
  1262. DDI configuration:
  1263. Connector - HDMI
  1264. Aux - Aux3
  1265. Hdp - Hdp3
  1266. <---------- Silicon Config End ---------->
  1267. <---------- Complex Config End ------------>
  1268. <-------------- PCIe Config End-------------->
  1269. PcieConfigurationInit Exit [0x0]
  1270. PcieEarlyInterfaceTN Enter
  1271.  
  1272. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1273.  
  1274.  
  1275. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1276.  
  1277.  
  1278. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1279.  
  1280.  
  1281. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1282.  
  1283. PcieEarlyInitTN Enter
  1284. PcieFP2CriteriaTN Enter
  1285. R WRITE Space TYPE_D0F0xBC Address 0x1F39C, Value 0x17080003
  1286.  
  1287. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1288.  
  1289.  
  1290. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1291.  
  1292. GnbSmuServiceRequestV4 Enter
  1293. Service Request 2
  1294.  
  1295. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1296.  
  1297. GnbSmuServiceRequestV4 Exit
  1298. GnbSmuServiceRequestV4 Enter
  1299. Service Request 3
  1300.  
  1301. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1302.  
  1303. GnbSmuServiceRequestV4 Exit
  1304.  
  1305. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1306.  
  1307.  
  1308. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1309.  
  1310. PciePifApplyGanging Enter
  1311. PciePifApplyGanging Exit
  1312. PciePhyApplyGanging Enter
  1313. PciePhyApplyGanging Exit
  1314. R WRITE Space TYPE_D0F0xBC Address 0x1F39C, Value 0x7040003
  1315.  
  1316. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1317.  
  1318.  
  1319. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1320.  
  1321. GnbSmuServiceRequestV4 Enter
  1322. Service Request 2
  1323.  
  1324. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1325.  
  1326. GnbSmuServiceRequestV4 Exit
  1327. GnbSmuServiceRequestV4 Enter
  1328. Service Request 3
  1329.  
  1330. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1331.  
  1332. GnbSmuServiceRequestV4 Exit
  1333.  
  1334. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1335.  
  1336.  
  1337. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1338.  
  1339. PciePifApplyGanging Enter
  1340. PciePifApplyGanging Exit
  1341. PciePhyApplyGanging Enter
  1342. PciePhyApplyGanging Exit
  1343. PciePifApplyGanging Enter
  1344. PciePifApplyGanging Exit
  1345. PciePhyApplyGanging Enter
  1346. PciePhyApplyGanging Exit
  1347. PciePifApplyGanging Enter
  1348. PciePifApplyGanging Exit
  1349. PciePhyApplyGanging Enter
  1350. PciePhyApplyGanging Exit
  1351. PciePhyLetPllPersonalityInitCallbackTN Enter
  1352. PciePifSetPllRampTime Enter
  1353. PciePifSetPllRampTime Exit
  1354.  
  1355. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1356.  
  1357.  
  1358. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1359.  
  1360.  
  1361. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1362.  
  1363.  
  1364. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1365.  
  1366. PciePhyLetPllPersonalityInitCallbackTN Exit
  1367. PciePhyLetPllPersonalityInitCallbackTN Enter
  1368. PciePifSetPllRampTime Enter
  1369. PciePifSetPllRampTime Exit
  1370.  
  1371. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1372.  
  1373.  
  1374. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1375.  
  1376.  
  1377. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1378.  
  1379.  
  1380. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1381.  
  1382. PciePhyLetPllPersonalityInitCallbackTN Exit
  1383. PciePhyLetPllPersonalityInitCallbackTN Enter
  1384. PciePifSetPllRampTime Enter
  1385. PciePifSetPllRampTime Exit
  1386.  
  1387. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1388.  
  1389.  
  1390. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1391.  
  1392.  
  1393. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1394.  
  1395.  
  1396. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1397.  
  1398. PciePhyLetPllPersonalityInitCallbackTN Exit
  1399. PciePhyLetPllPersonalityInitCallbackTN Enter
  1400. PciePifSetPllRampTime Enter
  1401. PciePifSetPllRampTime Exit
  1402.  
  1403. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1404.  
  1405.  
  1406. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1407.  
  1408.  
  1409. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1410.  
  1411.  
  1412. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1413.  
  1414. PciePhyLetPllPersonalityInitCallbackTN Exit
  1415. PcieOscInitTN Enter
  1416. OSC Mode - Fuses
  1417. OSC Mode From Fuses - Skip
  1418. PcieOscInitTN Exit
  1419. PciePhyLaneInitInitCallbackTN Enter
  1420. PciePhyLaneInitInitCallbackTN Exit
  1421. PciePhyLaneInitInitCallbackTN Enter
  1422. PciePhyLaneInitInitCallbackTN Exit
  1423. PciePhyLaneInitInitCallbackTN Enter
  1424. PciePhyLaneInitInitCallbackTN Exit
  1425. PciePhyLaneInitInitCallbackTN Enter
  1426. PciePhyLaneInitInitCallbackTN Exit
  1427. PcieEarlyInitCallbackTN Enter
  1428. Core Configuration: Wrapper [GFX], CoreID [2] - 1x16
  1429. PcieTopologyApplyLaneMux Enter
  1430. PcieTopologyApplyLaneMux Exit
  1431. PciePifSetRxDetectPowerMode Enter
  1432. PciePifSetRxDetectPowerMode Enter
  1433. PciePifSetLs2ExitTime Enter
  1434. PciePifSetLs2ExitTime Exit
  1435. PcieTopologySelectMasterPll Enter
  1436. PcieTopologySelectMasterPll Exit
  1437. PcieTopologySetLinkReversal Enter
  1438. PcieTopologySetLinkReversal Exit
  1439. PciePifPllPowerDown Enter
  1440. PciePifPllPowerDown Exit
  1441. PciePifPllInitForDdi Enter
  1442. PciePifPllInitForDdi Exit
  1443. PciePwrPowerDownDdiPllsV4 Enter
  1444. PciePwrPowerDownDdiPllsV4 Exit
  1445.  
  1446. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1447.  
  1448.  
  1449. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1450.  
  1451. PcieSetDdiOwnPhyV4 Enter
  1452. PcieSetDdiOwnPhyV4 Exit
  1453. PciePhyAvertClockPickers Enter
  1454. PciePhyAvertClockPickers Exit
  1455. PcieEarlyCoreInitTN Enter
  1456. PcieEarlyCoreInitTN Exit
  1457. PcieSetDllCapTN Enter
  1458. Read D18F3x1FC value 90E074F
  1459. Executing DLL configuration
  1460. Reading 0x4010 from PHY_SPACE 1214010
  1461. Read 4010 value = 1
  1462. Reading 0x4011 from PHY_SPACE 1214011
  1463. Read 4011 value = 1007
  1464. FuseFuncDllProcessCompCtl 0
  1465. Setting Gen1Index from switch case...case 2 - using 0xa
  1466. Set Gen1Index to A
  1467. Gen2Index - using DllProcFreqCtlIndex2Rate50 = 4
  1468. Set Gen2Index to 4
  1469. PcieSetDllCapTN Exit
  1470. PcieEarlyInitCallbackTN Exit [0]
  1471. PcieEarlyInitCallbackTN Enter
  1472. Core Configuration: Wrapper [GPPSB], CoreID [1] - 1x4, 1x4
  1473. PcieTopologyApplyLaneMux Enter
  1474. PcieTopologyApplyLaneMux Exit
  1475. PciePifSetRxDetectPowerMode Enter
  1476. PciePifSetRxDetectPowerMode Enter
  1477. PciePifSetLs2ExitTime Enter
  1478. PciePifSetLs2ExitTime Exit
  1479. PcieTopologySelectMasterPll Enter
  1480. PcieTopologySelectMasterPll Exit
  1481. PcieTopologyExecuteReconfigV4 Enter
  1482. GnbSmuServiceRequestV4 Enter
  1483. Service Request 25
  1484. GnbSmuServiceRequestV4 Exit
  1485. PcieTopologyExecuteReconfigV4 Exit
  1486. PcieTopologySetLinkReversal Enter
  1487. PcieTopologySetLinkReversal Exit
  1488. PciePifPllPowerDown Enter
  1489. PciePifPllPowerDown Exit
  1490. PciePifPllInitForDdi Enter
  1491. PciePifPllInitForDdi Exit
  1492. PciePwrPowerDownDdiPllsV4 Enter
  1493. PciePwrPowerDownDdiPllsV4 Exit
  1494.  
  1495. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1496.  
  1497.  
  1498. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1499.  
  1500. PciePhyAvertClockPickers Enter
  1501. PciePhyAvertClockPickers Exit
  1502. PcieEarlyCoreInitTN Enter
  1503. PcieEarlyCoreInitTN Exit
  1504. PcieSetDllCapTN Enter
  1505. Read D18F3x1FC value 90E074F
  1506. Executing DLL configuration
  1507. Reading 0x4010 from PHY_SPACE 1204010
  1508. Read 4010 value = 1
  1509. Reading 0x4011 from PHY_SPACE 1204011
  1510. Read 4011 value = 1007
  1511. FuseFuncDllProcessCompCtl 0
  1512. Setting Gen1Index from switch case...case 2 - using 0xa
  1513. Set Gen1Index to A
  1514. Gen2Index - using DllProcFreqCtlIndex2Rate50 = 4
  1515. Set Gen2Index to 4
  1516. PcieSetDllCapTN Exit
  1517. PcieEarlyInitCallbackTN Exit [0]
  1518. PcieEarlyInitCallbackTN Enter
  1519. PcieTopologyApplyLaneMux Enter
  1520. PcieTopologyApplyLaneMux Exit
  1521. PciePifSetRxDetectPowerMode Enter
  1522. PciePifSetRxDetectPowerMode Enter
  1523. PciePifSetLs2ExitTime Enter
  1524. PciePifSetLs2ExitTime Exit
  1525. PcieTopologySelectMasterPll Enter
  1526. PcieTopologySelectMasterPll Exit
  1527. PcieTopologySetLinkReversal Enter
  1528. PcieTopologySetLinkReversal Exit
  1529. PciePifPllPowerDown Enter
  1530. PciePifPllPowerDown Exit
  1531. PciePifPllInitForDdi Enter
  1532. PciePifPllInitForDdi Exit
  1533. PciePwrPowerDownDdiPllsV4 Enter
  1534. PciePwrPowerDownDdiPllsV4 Exit
  1535.  
  1536. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1537.  
  1538.  
  1539. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1540.  
  1541. PcieSetDdiOwnPhyV4 Enter
  1542. PcieSetDdiOwnPhyV4 Exit
  1543. PciePhyAvertClockPickers Enter
  1544. PciePhyAvertClockPickers Exit
  1545. PcieEarlyInitCallbackTN Exit [0]
  1546. PcieEarlyInitCallbackTN Enter
  1547. PcieTopologyApplyLaneMux Enter
  1548. PcieTopologyApplyLaneMux Exit
  1549. PciePifSetRxDetectPowerMode Enter
  1550. PciePifSetRxDetectPowerMode Enter
  1551. PciePifSetLs2ExitTime Enter
  1552. PciePifSetLs2ExitTime Exit
  1553. PcieTopologySelectMasterPll Enter
  1554. PcieTopologySelectMasterPll Exit
  1555. PcieTopologySetLinkReversal Enter
  1556. PcieTopologySetLinkReversal Exit
  1557. PciePifPllPowerDown Enter
  1558.  
  1559. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1560.  
  1561.  
  1562. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1563.  
  1564. PciePifPllPowerDown Exit
  1565. PciePifPllInitForDdi Enter
  1566. PciePifPllInitForDdi Exit
  1567. PciePwrPowerDownDdiPllsV4 Enter
  1568. PciePwrPowerDownDdiPllsV4 Exit
  1569.  
  1570. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1571.  
  1572.  
  1573. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1574.  
  1575. PcieSetDdiOwnPhyV4 Enter
  1576. PcieSetDdiOwnPhyV4 Exit
  1577. PciePhyAvertClockPickers Enter
  1578. PciePhyAvertClockPickers Exit
  1579. PcieEarlyInitCallbackTN Exit [0]
  1580. PcieSetVoltageTN Enter
  1581.  
  1582. * BOUNDS_CHK Event: 08040100 Data: A021, 0, 0, 0
  1583.  
  1584. Set Voltage for Gen 1, Vid code 96
  1585. R WRITE Space TYPE_GMM Address 0x063C, Value 0x0000
  1586.  
  1587. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1588.  
  1589.  
  1590. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1591.  
  1592. R WRITE Space TYPE_GMM Address 0x063C, Value 0x6004
  1593.  
  1594. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1595.  
  1596.  
  1597. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1598.  
  1599. PcieSetVoltageTN Exit
  1600. PcieEarlyInitTN Exit [0]
  1601. PcieEarlyPortInitCallbackTN Enter
  1602. PcieEarlyPortInitCallbackTN Exit
  1603. PcieEarlyPortInitCallbackTN Enter
  1604. PcieEarlyPortInitCallbackTN Exit
  1605. PcieEarlyPortInitCallbackTN Enter
  1606. PcieEarlyPortInitCallbackTN Exit
  1607. PcieTraining Enter
  1608. Port 0:2:0 State [LinkTrainingResetTimeout ] Time Stamp [4396893]
  1609. Port 0:4:0 State [LinkTrainingResetTimeout ] Time Stamp [4403047]
  1610. Port 0:8:0 State [LinkStateTrainingComplete] Time Stamp [0]
  1611. Port 0:2:0 State [LinkStateReleaseTraining ] Time Stamp [4396893]
  1612. Port 0:4:0 State [LinkStateReleaseTraining ] Time Stamp [4403047]
  1613. Port 0:2:0 State [LinkStateDetectPresence ] Time Stamp [4426847]
  1614. Port 0:4:0 State [LinkStateDetectPresence ] Time Stamp [4432800]
  1615. Port 0:2:0 State [LinkStateDeviceNotPresent] Time Stamp [4426847]
  1616. Port 0:4:0 State [LinkStateDeviceNotPresent] Time Stamp [4432800]
  1617. Port 0:2:0 State [LinkStateTrainingComplete] Time Stamp [4426847]
  1618. Port 0:4:0 State [LinkStateTrainingComplete] Time Stamp [4432800]
  1619. PcieTraining Exit [0]
  1620. PcieSiliconHidePorts Enter
  1621.  
  1622. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1623.  
  1624.  
  1625. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1626.  
  1627.  
  1628. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1629.  
  1630.  
  1631. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1632.  
  1633. Write D0F0x64_x0C.Value = FC
  1634. PcieSiliconHidePorts Exit
  1635. PcieEarlyInterfaceTN Exit [0x0]
  1636.  
  1637. AmdInitEarly: End
  1638.  
  1639. Got past agesawrapper_amdinitearly
  1640. AmdInitPost: Start
  1641.  
  1642. PciePostEarlyInterfaceTN Enter
  1643.  
  1644. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1645.  
  1646.  
  1647. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1648.  
  1649.  
  1650. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1651.  
  1652.  
  1653. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1654.  
  1655. PcieTraining Enter
  1656. PcieTraining Exit [0]
  1657. PcieSiliconHidePorts Enter
  1658.  
  1659. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1660.  
  1661.  
  1662. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1663.  
  1664.  
  1665. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1666.  
  1667.  
  1668. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  1669.  
  1670. Write D0F0x64_x0C.Value = FC
  1671. PcieSiliconHidePorts Exit
  1672. PciePostEarlyInterfaceTN Exit [0x0]
  1673. GfxConfigPostInterface Enter
  1674. <-------------- GFX Config Start ------------->
  1675. HD Audio - Enabled
  1676. DynamicRefreshRate - 0x0
  1677. LcdBackLightControl - 0xC8
  1678. AbmSupport - Disabled
  1679. GmcClockGating - Enabled
  1680. GmcPowerGating - GmcPowerGatingWidthStutter
  1681. UmaSteering - excel992
  1682. iGpuVgaMode - VGA
  1683. UmaMode - No UMA
  1684. <-------------- GFX Config End --------------->
  1685. GfxConfigPostInterface Exit [0x0]
  1686. GfxPostInterfaceTN Enter
  1687. GfxGetDiscreteCardInfo Enter
  1688. Evaluate device [0:17:0]
  1689. Evaluate device [0:18:0]
  1690. Evaluate device [0:18:2]
  1691. Evaluate device [0:19:0]
  1692. Evaluate device [0:19:2]
  1693. Evaluate device [0:20:0]
  1694. Evaluate device [0:20:2]
  1695. Evaluate device [0:20:3]
  1696. Evaluate device [0:20:4]
  1697. Evaluate device [0:24:0]
  1698. Evaluate device [0:24:1]
  1699. Evaluate device [0:24:2]
  1700. Evaluate device [0:24:3]
  1701. Evaluate device [0:24:4]
  1702. Evaluate device [0:24:5]
  1703. GfxGetDiscreteCardInfo Exit
  1704. GfxPostInterfaceTN Exit [0x0]
  1705. AmdMemAuto: Start
  1706. MEM PARAMS:
  1707. BottomIo : 00E0
  1708. MemHoleRemap : 1
  1709. LimitBelow1TB : 1
  1710. UserTimingMode : 0
  1711. MemClockValue : 800
  1712. BankIntlv : 1
  1713. NodeIntlv : 0
  1714. ChannelIntlv : 1
  1715. EccFeature : 0
  1716. PowerDown : 1
  1717. OnLineSpare : 0
  1718. Parity : 0
  1719. BankSwizzle : 1
  1720. MemClr : 1
  1721. UmaMode : 1
  1722. UmaSize : 8192
  1723. MemRestoreCtl : 0
  1724. SaveMemContextCtl : 0
  1725. ExternalVrefCtl : 0
  1726. ForceTrainMode : 2
  1727.  
  1728. F15TnGetPstateFrequency - P3
  1729. FrequencyInMHz=3900, CpuFid=23, CpuDid=0
  1730. SPD Socket 0 Channel 1 Dimm 1: 00400F84
  1731.  
  1732. * BOUNDS_CHK Event: 08040100 Data: 1247000, 0, 0, 0
  1733.  
  1734. MemFInitTableDrive [0000000000000000] Start
  1735. MemFInitTableDrive End
  1736.  
  1737. Maximize Performance
  1738. Node0 DCT1 Channel0 Dimm1 VDD Byte: 0x00
  1739.  
  1740. Commonly supported VDDIO is: 1.5V, .
  1741. F15TnGetNbPstateInfo - NB P3
  1742. F15TnGetNbPstateInfo - NB P2
  1743. F15TnGetNbPstateInfo - NB P1
  1744. F15TnGetNbPstateInfo - NB P0
  1745. En:1 Fid:E Did:0 Vid:44
  1746. F15TnGetNbFreqNumeratorInMHz - NbFid=14
  1747. FreqNumeratorInMHz=1800
  1748. F15TnGetNbFreqDivisor - NbDid=0
  1749. FreqDivisor=1
  1750. F15TnCovertVidInuV
  1751. Vid=44, VoltageInuV=1125000
  1752. NB Pstate 0 is Valid. NbVid=68 VoltageInuV=1125000
  1753.  
  1754. Start NB Pstate voltage adjustment.
  1755. D0F0xBC_xE0104168: 199A9BBB
  1756. D0F0xBC_xE010416C: 10931618
  1757. D0F0xBC_xE0104170: 000A8D10
  1758. Original MemClkVidLo: 6E
  1759. Original MemClkVidHi: 60
  1760. Add 25mV
  1761. Adjusted MemClkVidLo: 6A
  1762. Adjusted MemClkVidHi: 5C
  1763. NBPs NbVid MemPstate Override
  1764. 0 44 0 No change
  1765.  
  1766. Check speed supported for each VDDIO for Node0 DCT1: 1.5V -> 933MHz
  1767. MemFInitTableDrive [0000000000000001] Start
  1768. MemFInitTableDrive End
  1769.  
  1770.  
  1771. Enable Per Rank Training....
  1772.  
  1773. MemFInitTableDrive [0000000000000002] Start
  1774. MemFInitTableDrive End
  1775. MemFInitTableDrive [0000000000000003] Start
  1776. MemFInitTableDrive End
  1777.  
  1778. Searching for VDDIO that can maximize frequency:
  1779. Node0: 1.5V -> 667MHz, 1.35V -> 0MHz, 1.25V -> 0MHz
  1780. Number of nodes that can run at maximize performance: 1.5V -> 1 Nodes 1.35V -> 0 Nodes 1.25V -> 0 Nodes.
  1781.  
  1782. Calling out to Platform BIOS on Socket 0, Module 0...
  1783.  
  1784. VDDIO = 1.5V
  1785. F15TnGetNbPstateInfo - NB P0
  1786. En:1 Fid:E Did:0 Vid:44
  1787. F15TnGetNbFreqNumeratorInMHz - NbFid=14
  1788. FreqNumeratorInMHz=1800
  1789. F15TnGetNbFreqDivisor - NbDid=0
  1790. FreqDivisor=1
  1791. F15TnCovertVidInuV
  1792. Vid=44, VoltageInuV=1125000
  1793. NB Pstate 0 is Valid. NbVid=68 VoltageInuV=1125000
  1794. NB P0: 1800MHz
  1795. F15TnGetPstateFrequency - P3
  1796. FrequencyInMHz=3900, CpuFid=23, CpuDid=0
  1797. Memclk Freq: 333
  1798. RdPtr: 6
  1799. MemFInitTableDrive [0000000000000010] Start
  1800. MemFInitTableDrive End
  1801. Dct 1
  1802. FenceThresholdTxDll
  1803. Seeds: 13 13 13 13 13 13 13 13 13
  1804. PhyFenceTrEn = 1
  1805. PRE: 1B 1D 1C 1C 1C 1D 1C 1B 1B
  1806. Fence: 14
  1807.  
  1808. FenceThresholdRxDll
  1809. Seeds: 13 13 13 13 13 13 13 13 13
  1810. PhyFenceTrEn = 1
  1811. PRE: 1C 1B 1C 1C 1C 1C 1C 1C 1C
  1812. Fence: 14
  1813.  
  1814. FenceThresholdTxPad
  1815. Seeds: 13 13 13 13 13 13 13 13 13
  1816. PhyFenceTrEn = 1
  1817. PRE: 1C 1D 1C 1C 1C 1D 1C 1C 1C
  1818. Fence: 15
  1819.  
  1820. MemClkFreq: 333 MHz
  1821.  
  1822. Start Dram Init
  1823. EnDramInit = 1 for both DCTs
  1824. Dct 1
  1825. CS 2
  1826. CS2 MR2 00080
  1827. CS2 MR3 00000
  1828. CS2 MR1 00042
  1829. CS2 MR0 01329
  1830. End Dram Init
  1831.  
  1832. TOP_MEM: 0000E0000000
  1833. TOP_MEM2: 000120000000
  1834. Sub1THoleBase: 000000000000
  1835. MemFInitTableDrive [0000000000000004] Start
  1836. MemFInitTableDrive End
  1837.  
  1838. Start Mem Restore
  1839. Mem Restore Fails!
  1840.  
  1841. Start serial training
  1842. Node 0
  1843.  
  1844. Calling out to Platform BIOS...
  1845. MemFInitTableDrive [0000000000000007] Start
  1846. MemFInitTableDrive End
  1847.  
  1848. Start write leveling
  1849. Dct 0
  1850. Dct 1
  1851. CS 2
  1852. CS2 MR1 000C2
  1853. CS2 MR2 00080
  1854. CS3 MR1 010C2 swapped to -> CS3 MR2 01122
  1855. CS3 MR2 00080 swapped to -> CS3 MR1 00100
  1856.  
  1857. Byte: 00 01 02 03 04 05 06 07 ECC
  1858. Seeds: 55 55 55 55 55 55 55 55 55
  1859. WrtLvTrEn = 1
  1860. PRE: 48 4B 4F 52 57 5A 5C 5D
  1861. WrDqs: 08 0B 0F 12 17 1A 1C 1D
  1862.  
  1863. CS2 MR1 00042
  1864. CS2 MR2 00080
  1865. CS3 MR1 00042 swapped to -> CS3 MR2 00022
  1866. CS3 MR2 00080 swapped to -> CS3 MR1 00100
  1867. CS 3
  1868. CS2 MR1 010C2
  1869. CS2 MR2 00080
  1870. CS3 MR1 000C2 swapped to -> CS3 MR2 00122
  1871. CS3 MR2 00080 swapped to -> CS3 MR1 00100
  1872.  
  1873. Byte: 00 01 02 03 04 05 06 07 ECC
  1874. Seeds: 55 55 55 55 55 55 55 55 55
  1875. WrtLvTrEn = 1
  1876. PRE: 48 4D 51 53 58 5C 5E 5F
  1877. WrDqs: 08 0D 11 13 18 1C 1E 1F
  1878.  
  1879. CS2 MR1 00042
  1880. CS2 MR2 00080
  1881. CS3 MR1 00042 swapped to -> CS3 MR2 00022
  1882. CS3 MR2 00080 swapped to -> CS3 MR1 00100
  1883. End write leveling
  1884.  
  1885. MemFInitTableDrive [0000000000000008] Start
  1886. MemFInitTableDrive End
  1887.  
  1888. Start HW RxEn training
  1889. Dct 0
  1890. Dct 1
  1891. CS 2
  1892. TestAddr 200000
  1893. Byte: 00 01 02 03 04 05 06 07 ECC
  1894. SeedValue: 032 032 032 032 032 032 032 032
  1895. SeedTotal: 03A 03D 041 044 049 04C 04E 04F
  1896. SeedPRE: 03A 03D 041 044 049 04C 04E 04F
  1897. PRE: 045 047 049 04C 04F 051 056 05B
  1898. RxEn: 065 067 069 06C 06F 071 076 07B
  1899.  
  1900. CS 3
  1901. TestAddr 80200000
  1902. Byte: 00 01 02 03 04 05 06 07 ECC
  1903. SeedValue: 032 032 032 032 032 032 032 032
  1904. SeedTotal: 03A 03F 043 045 04A 04E 050 051
  1905. SeedPRE: 03A 03F 043 045 04A 04E 050 051
  1906. PRE: 046 048 049 04E 04F 052 057 05C
  1907. RxEn: 066 068 069 06E 06F 072 077 07C
  1908.  
  1909. End HW RxEn training
  1910.  
  1911. MemFInitTableDrive [0000000000000009] Start
  1912. MemFInitTableDrive End
  1913. Dct 0
  1914. Dct 1
  1915. MaxRdLat: 04C
  1916. MemFInitTableDrive [000000000000000D] Start
  1917. MemFInitTableDrive End
  1918.  
  1919. Start Read/Write Data Eye Edge Detection.
  1920. Dct 0
  1921. Dct 1
  1922. CS 2
  1923. Increase WrDat, Train RdDqs:
  1924.  
  1925. Write Delay: 10
  1926.  
  1927. Start HW RxEn Seedless training
  1928.  
  1929. Chip Select: 02
  1930. Byte: 00 01 02 03 04 05 06 07 ECC
  1931. RxEn Orig: 065 067 069 06C 06F 071 076 07B
  1932. i: 00
  1933.  
  1934. j: 00
  1935. Byte: 00 01 02 03 04 05 06 07 ECC
  1936. Target BL Found: N N N N N N N N
  1937. Target BL Value: 000 000 000 000 000 000 000 000
  1938. Setting PassTestRxEnDly
  1939. PassTestRxEnDly: 075 077 079 07C 07F 081 086 08B
  1940. OutOfRange: N N N N N N N N
  1941. Checking if PassTestRxEnDly Passes?
  1942.  
  1943. MaxRdLat: 04E
  1944. TestAddr: 200000
  1945. STAGE: 0 Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.
  1946.  
  1947. Byte Lane : 08 07 06 05 04 03 02 01 00
  1948. DQS Delays : 00 00 00 00 00 00 00 00 00
  1949. Result : P P P P P P P P P
  1950. ResultFound : Y
  1951.  
  1952. Byte Lane : 08 07 06 05 04 03 02 01 00
  1953. DQS Delays : 00 1C 1C 1C 1C 1C 1C 1C 1C
  1954. Result : . . . . . . . .
  1955. ResultFound : Y Y Y Y Y Y Y Y Y
  1956.  
  1957. STAGE: 1 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.
  1958.  
  1959. Byte Lane : 08 07 06 05 04 03 02 01 00
  1960. DQS Delays : 00 1D 1D 1D 1D 1D 1D 1D 1D
  1961. Result : P . . . . . . . .
  1962. ResultFound : Y
  1963.  
  1964. Byte Lane : 08 07 06 05 04 03 02 01 00
  1965. DQS Delays : 00 1E 1E 1E 1E 1E 1E 1E 1E
  1966. Result : . . . . . . . .
  1967. ResultFound : Y
  1968.  
  1969. Byte Lane : 08 07 06 05 04 03 02 01 00
  1970. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  1971. Result : P P . P . . P .
  1972. ResultFound : Y Y Y Y Y
  1973.  
  1974. Byte Lane : 08 07 06 05 04 03 02 01 00
  1975. DQS Delays : 00 1F 1F 00 1F 00 00 1F 00
  1976. Result : P P P P
  1977. ResultFound : Y Y Y Y Y Y Y Y Y
  1978.  
  1979. STAGE: 2 Sweeping Read DQS, decrementing from 1F by 04, until all bytelanes PASS.
  1980.  
  1981. Byte Lane : 08 07 06 05 04 03 02 01 00
  1982. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  1983. Result : P . . . . . . . .
  1984. ResultFound : Y
  1985.  
  1986. Byte Lane : 08 07 06 05 04 03 02 01 00
  1987. DQS Delays : 00 1B 1B 1B 1B 1B 1B 1B 1B
  1988. Result : . . . . . . . .
  1989. ResultFound : Y
  1990.  
  1991. Byte Lane : 08 07 06 05 04 03 02 01 00
  1992. DQS Delays : 00 17 17 17 17 17 17 17 17
  1993. Result : P P P P P P P P
  1994. ResultFound : Y Y Y Y Y Y Y Y Y
  1995.  
  1996. STAGE: 3 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.
  1997.  
  1998. Byte Lane : 08 07 06 05 04 03 02 01 00
  1999. DQS Delays : 00 18 18 18 18 18 18 18 18
  2000. Result : P P P P P P P P P
  2001. ResultFound : Y
  2002.  
  2003. Byte Lane : 08 07 06 05 04 03 02 01 00
  2004. DQS Delays : 00 19 19 19 19 19 19 19 19
  2005. Result : P P P P P P P P
  2006. ResultFound : Y
  2007.  
  2008. Byte Lane : 08 07 06 05 04 03 02 01 00
  2009. DQS Delays : 00 1A 1A 1A 1A 1A 1A 1A 1A
  2010. Result : . P . P . P . .
  2011. ResultFound : Y Y Y Y Y Y
  2012.  
  2013. Byte Lane : 08 07 06 05 04 03 02 01 00
  2014. DQS Delays : 00 1A 1B 1A 1B 1A 1B 1A 1A
  2015. Result : . . .
  2016. ResultFound : Y Y Y Y Y Y Y Y Y
  2017.  
  2018. Data Eye Results:
  2019.  
  2020. Byte Left Right
  2021. Lane Edge Edge Width Center
  2022. 0 00 19 19 0D
  2023. 1 1F 19 1A 0C
  2024. 2 00 1A 1A 0D
  2025. 3 00 19 19 0D
  2026. 4 1F 1A 1B 0D
  2027. 5 00 19 19 0D
  2028. 6 1F 1A 1B 0D
  2029. 7 1F 19 1A 0C
  2030.  
  2031. Byte: 00 01 02 03 04 05 06 07 ECC
  2032. Err Status: P P P P P P P P
  2033. Byte: 00 01 02 03 04 05 06 07 ECC
  2034. FailTestRxEnDly: 0B5 0B7 0B9 0BC 0BF 0C1 0C6 0CB
  2035. Setting FailTestRxEnDly
  2036. OutOfRange: N N N N N N N N
  2037. FailTestRxEnDly: Y Y Y Y Y Y Y Y
  2038.  
  2039. Checking if FailTestRxEnDly Fails?
  2040. MaxRdLat: 054
  2041. TestAddr: 200000
  2042. STAGE: 0 Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.
  2043.  
  2044. Byte Lane : 08 07 06 05 04 03 02 01 00
  2045. DQS Delays : 00 00 00 00 00 00 00 00 00
  2046. Result : P . . . . . . . .
  2047. ResultFound : Y Y Y Y Y Y Y Y Y
  2048.  
  2049. STAGE: 1 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.
  2050.  
  2051. Byte Lane : 08 07 06 05 04 03 02 01 00
  2052. DQS Delays : 00 01 01 01 01 01 01 01 01
  2053. Result : P . . . . . . . .
  2054. ResultFound : Y
  2055.  
  2056. Byte Lane : 08 07 06 05 04 03 02 01 00
  2057. DQS Delays : 00 02 02 02 02 02 02 02 02
  2058. Result : . . . . . . . .
  2059. ResultFound : Y
  2060.  
  2061. Byte Lane : 08 07 06 05 04 03 02 01 00
  2062. DQS Delays : 00 03 03 03 03 03 03 03 03
  2063. Result : . . . . . . . .
  2064. ResultFound : Y
  2065.  
  2066. Byte Lane : 08 07 06 05 04 03 02 01 00
  2067. DQS Delays : 00 04 04 04 04 04 04 04 04
  2068. Result : . . . . . . . .
  2069. ResultFound : Y
  2070.  
  2071. Byte Lane : 08 07 06 05 04 03 02 01 00
  2072. DQS Delays : 00 05 05 05 05 05 05 05 05
  2073. Result : . . . . . . . .
  2074. ResultFound : Y
  2075.  
  2076. Byte Lane : 08 07 06 05 04 03 02 01 00
  2077. DQS Delays : 00 06 06 06 06 06 06 06 06
  2078. Result : . . . . . . . .
  2079. ResultFound : Y
  2080.  
  2081. Byte Lane : 08 07 06 05 04 03 02 01 00
  2082. DQS Delays : 00 07 07 07 07 07 07 07 07
  2083. Result : . . . . . . . .
  2084. ResultFound : Y
  2085.  
  2086. Byte Lane : 08 07 06 05 04 03 02 01 00
  2087. DQS Delays : 00 08 08 08 08 08 08 08 08
  2088. Result : . . . . . . . .
  2089. ResultFound : Y
  2090.  
  2091. Byte Lane : 08 07 06 05 04 03 02 01 00
  2092. DQS Delays : 00 09 09 09 09 09 09 09 09
  2093. Result : . . . . . . . .
  2094. ResultFound : Y
  2095.  
  2096. Byte Lane : 08 07 06 05 04 03 02 01 00
  2097. DQS Delays : 00 0A 0A 0A 0A 0A 0A 0A 0A
  2098. Result : . . . . . . . .
  2099. ResultFound : Y
  2100.  
  2101. Byte Lane : 08 07 06 05 04 03 02 01 00
  2102. DQS Delays : 00 0B 0B 0B 0B 0B 0B 0B 0B
  2103. Result : . . . . . . . .
  2104. ResultFound : Y
  2105.  
  2106. Byte Lane : 08 07 06 05 04 03 02 01 00
  2107. DQS Delays : 00 0C 0C 0C 0C 0C 0C 0C 0C
  2108. Result : . . . . . . . .
  2109. ResultFound : Y
  2110.  
  2111. Byte Lane : 08 07 06 05 04 03 02 01 00
  2112. DQS Delays : 00 0D 0D 0D 0D 0D 0D 0D 0D
  2113. Result : . . . . . . . .
  2114. ResultFound : Y
  2115.  
  2116. Byte Lane : 08 07 06 05 04 03 02 01 00
  2117. DQS Delays : 00 0E 0E 0E 0E 0E 0E 0E 0E
  2118. Result : . . . . . . . .
  2119. ResultFound : Y
  2120.  
  2121. Byte Lane : 08 07 06 05 04 03 02 01 00
  2122. DQS Delays : 00 0F 0F 0F 0F 0F 0F 0F 0F
  2123. Result : . . . . . . . .
  2124. ResultFound : Y
  2125.  
  2126. Byte Lane : 08 07 06 05 04 03 02 01 00
  2127. DQS Delays : 00 10 10 10 10 10 10 10 10
  2128. Result : . . . . . . . .
  2129. ResultFound : Y
  2130.  
  2131. Byte Lane : 08 07 06 05 04 03 02 01 00
  2132. DQS Delays : 00 11 11 11 11 11 11 11 11
  2133. Result : . . . . . . . .
  2134. ResultFound : Y
  2135.  
  2136. Byte Lane : 08 07 06 05 04 03 02 01 00
  2137. DQS Delays : 00 12 12 12 12 12 12 12 12
  2138. Result : . . . . . . . .
  2139. ResultFound : Y
  2140.  
  2141. Byte Lane : 08 07 06 05 04 03 02 01 00
  2142. DQS Delays : 00 13 13 13 13 13 13 13 13
  2143. Result : . . . . . . . .
  2144. ResultFound : Y
  2145.  
  2146. Byte Lane : 08 07 06 05 04 03 02 01 00
  2147. DQS Delays : 00 14 14 14 14 14 14 14 14
  2148. Result : . . . . . . . .
  2149. ResultFound : Y
  2150.  
  2151. Byte Lane : 08 07 06 05 04 03 02 01 00
  2152. DQS Delays : 00 15 15 15 15 15 15 15 15
  2153. Result : . . . . . . . .
  2154. ResultFound : Y
  2155.  
  2156. Byte Lane : 08 07 06 05 04 03 02 01 00
  2157. DQS Delays : 00 16 16 16 16 16 16 16 16
  2158. Result : . . . . . . . .
  2159. ResultFound : Y
  2160.  
  2161. Byte Lane : 08 07 06 05 04 03 02 01 00
  2162. DQS Delays : 00 17 17 17 17 17 17 17 17
  2163. Result : . . . . . . . .
  2164. ResultFound : Y
  2165.  
  2166. Byte Lane : 08 07 06 05 04 03 02 01 00
  2167. DQS Delays : 00 18 18 18 18 18 18 18 18
  2168. Result : . . . . . . . .
  2169. ResultFound : Y
  2170.  
  2171. Byte Lane : 08 07 06 05 04 03 02 01 00
  2172. DQS Delays : 00 19 19 19 19 19 19 19 19
  2173. Result : . . . . . . . .
  2174. ResultFound : Y
  2175.  
  2176. Byte Lane : 08 07 06 05 04 03 02 01 00
  2177. DQS Delays : 00 1A 1A 1A 1A 1A 1A 1A 1A
  2178. Result : . . . . . . . .
  2179. ResultFound : Y
  2180.  
  2181. Byte Lane : 08 07 06 05 04 03 02 01 00
  2182. DQS Delays : 00 1B 1B 1B 1B 1B 1B 1B 1B
  2183. Result : . . . . . . . .
  2184. ResultFound : Y
  2185.  
  2186. Byte Lane : 08 07 06 05 04 03 02 01 00
  2187. DQS Delays : 00 1C 1C 1C 1C 1C 1C 1C 1C
  2188. Result : . . . . . . . .
  2189. ResultFound : Y
  2190.  
  2191. Byte Lane : 08 07 06 05 04 03 02 01 00
  2192. DQS Delays : 00 1D 1D 1D 1D 1D 1D 1D 1D
  2193. Result : . . . . . . . .
  2194. ResultFound : Y
  2195.  
  2196. Byte Lane : 08 07 06 05 04 03 02 01 00
  2197. DQS Delays : 00 1E 1E 1E 1E 1E 1E 1E 1E
  2198. Result : . . . . . . . .
  2199. ResultFound : Y
  2200.  
  2201. Byte Lane : 08 07 06 05 04 03 02 01 00
  2202. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  2203. Result : . . . . . . . .
  2204. ResultFound : Y
  2205.  
  2206. --DATA EYE NOT FOUND--
  2207.  
  2208.  
  2209. Byte: 00 01 02 03 04 05 06 07 ECC
  2210. Err Status: F F F F F F F F
  2211. Set FinalRxEnCycle: Y Y Y Y Y Y Y Y
  2212. OutOfRange: N N N N N N N N
  2213. FinalRxEnCycle: 065 067 069 06C 06F 071 076 07B
  2214. ByteLaneFail: Y Y Y Y Y Y Y Y
  2215. ByteLanePass: Y Y Y Y Y Y Y Y
  2216.  
  2217. Setting new RDQS based on FinalRxEnCycle
  2218.  
  2219. MaxRdLat: 04E
  2220. TestAddr: 200000
  2221. STAGE: 0 Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.
  2222.  
  2223. Byte Lane : 08 07 06 05 04 03 02 01 00
  2224. DQS Delays : 00 00 00 00 00 00 00 00 00
  2225. Result : P P P P P P P P P
  2226. ResultFound : Y
  2227.  
  2228. Byte Lane : 08 07 06 05 04 03 02 01 00
  2229. DQS Delays : 00 1C 1C 1C 1C 1C 1C 1C 1C
  2230. Result : . . . . . . . .
  2231. ResultFound : Y Y Y Y Y Y Y Y Y
  2232.  
  2233. STAGE: 1 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.
  2234.  
  2235. Byte Lane : 08 07 06 05 04 03 02 01 00
  2236. DQS Delays : 00 1D 1D 1D 1D 1D 1D 1D 1D
  2237. Result : P . . . . . . . .
  2238. ResultFound : Y
  2239.  
  2240. Byte Lane : 08 07 06 05 04 03 02 01 00
  2241. DQS Delays : 00 1E 1E 1E 1E 1E 1E 1E 1E
  2242. Result : . . . . . . . .
  2243. ResultFound : Y
  2244.  
  2245. Byte Lane : 08 07 06 05 04 03 02 01 00
  2246. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  2247. Result : P P . P . . P .
  2248. ResultFound : Y Y Y Y Y
  2249.  
  2250. Byte Lane : 08 07 06 05 04 03 02 01 00
  2251. DQS Delays : 00 1F 1F 00 1F 00 00 1F 00
  2252. Result : P P P P
  2253. ResultFound : Y Y Y Y Y Y Y Y Y
  2254.  
  2255. STAGE: 2 Sweeping Read DQS, decrementing from 1F by 04, until all bytelanes PASS.
  2256.  
  2257. Byte Lane : 08 07 06 05 04 03 02 01 00
  2258. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  2259. Result : P . . . . . . . .
  2260. ResultFound : Y
  2261.  
  2262. Byte Lane : 08 07 06 05 04 03 02 01 00
  2263. DQS Delays : 00 1B 1B 1B 1B 1B 1B 1B 1B
  2264. Result : . . . . . . . .
  2265. ResultFound : Y
  2266.  
  2267. Byte Lane : 08 07 06 05 04 03 02 01 00
  2268. DQS Delays : 00 17 17 17 17 17 17 17 17
  2269. Result : P P P P P P P P
  2270. ResultFound : Y Y Y Y Y Y Y Y Y
  2271.  
  2272. STAGE: 3 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.
  2273.  
  2274. Byte Lane : 08 07 06 05 04 03 02 01 00
  2275. DQS Delays : 00 18 18 18 18 18 18 18 18
  2276. Result : P P P P P P P P P
  2277. ResultFound : Y
  2278.  
  2279. Byte Lane : 08 07 06 05 04 03 02 01 00
  2280. DQS Delays : 00 19 19 19 19 19 19 19 19
  2281. Result : P P P P P P P P
  2282. ResultFound : Y
  2283.  
  2284. Byte Lane : 08 07 06 05 04 03 02 01 00
  2285. DQS Delays : 00 1A 1A 1A 1A 1A 1A 1A 1A
  2286. Result : . P . P . P . .
  2287. ResultFound : Y Y Y Y Y Y
  2288.  
  2289. Byte Lane : 08 07 06 05 04 03 02 01 00
  2290. DQS Delays : 00 1A 1B 1A 1B 1A 1B 1A 1A
  2291. Result : . . .
  2292. ResultFound : Y Y Y Y Y Y Y Y Y
  2293.  
  2294. Data Eye Results:
  2295.  
  2296. Byte Left Right
  2297. Lane Edge Edge Width Center
  2298. 0 00 19 19 0D
  2299. 1 1F 19 1A 0C
  2300. 2 00 1A 1A 0D
  2301. 3 00 19 19 0D
  2302. 4 1F 1A 1B 0D
  2303. 5 00 19 19 0D
  2304. 6 1F 1A 1B 0D
  2305. 7 1F 19 1A 0C
  2306.  
  2307.  
  2308. End HW RxEn Seedless training
  2309.  
  2310.  
  2311. Train WrDat:
  2312.  
  2313. STAGE: 0 Sweeping Write DQS, incrementing from 00 by 04, until all bytelanes PASS.
  2314.  
  2315. Byte Lane : 08 07 06 05 04 03 02 01 00
  2316. DQS Delays : 00 00 00 00 00 00 00 00 00
  2317. Result : P . . . . . . . .
  2318. ResultFound : Y
  2319.  
  2320. Byte Lane : 08 07 06 05 04 03 02 01 00
  2321. DQS Delays : 00 04 04 04 04 04 04 04 04
  2322. Result : P P P P P P P P
  2323. ResultFound : Y Y Y Y Y Y Y Y Y
  2324.  
  2325. STAGE: 1 Sweeping Write DQS, decrementing from Current Delay by 01, until all bytelanes FAIL.
  2326.  
  2327. Byte Lane : 08 07 06 05 04 03 02 01 00
  2328. DQS Delays : 00 03 03 03 03 03 03 03 03
  2329. Result : P P P P P P P P P
  2330. ResultFound : Y
  2331.  
  2332. Byte Lane : 08 07 06 05 04 03 02 01 00
  2333. DQS Delays : 00 02 02 02 02 02 02 02 02
  2334. Result : . P P P P P . .
  2335. ResultFound : Y Y Y Y
  2336.  
  2337. Byte Lane : 08 07 06 05 04 03 02 01 00
  2338. DQS Delays : 00 02 01 01 01 01 01 02 02
  2339. Result : . . . . P
  2340. ResultFound : Y Y Y Y Y Y Y Y
  2341.  
  2342. Byte Lane : 08 07 06 05 04 03 02 01 00
  2343. DQS Delays : 00 02 01 01 01 01 00 02 02
  2344. Result : .
  2345. ResultFound : Y Y Y Y Y Y Y Y Y
  2346.  
  2347. STAGE: 2 Sweeping Write DQS, decrementing from 1F by 04, until all bytelanes PASS.
  2348.  
  2349. Byte Lane : 08 07 06 05 04 03 02 01 00
  2350. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  2351. Result : P P . . . . . . .
  2352. ResultFound : Y Y
  2353.  
  2354. Byte Lane : 08 07 06 05 04 03 02 01 00
  2355. DQS Delays : 00 1F 1B 1B 1B 1B 1B 1B 1B
  2356. Result : P P P P P P P
  2357. ResultFound : Y Y Y Y Y Y Y Y Y
  2358.  
  2359. STAGE: 3 Sweeping Write DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.
  2360.  
  2361. Data Eye Results:
  2362.  
  2363. Byte Left Right
  2364. Lane Edge Edge Width Center
  2365. 0 03 1C 19 10
  2366. 1 03 1C 19 10
  2367. 2 01 1C 1B 0F
  2368. 3 02 1C 1A 0F
  2369. 4 02 1C 1A 0F
  2370. 5 02 1C 1A 0F
  2371. 6 02 1C 1A 0F
  2372. 7 03 1F 1C 11
  2373. CS 3
  2374. Increase WrDat, Train RdDqs:
  2375.  
  2376. Write Delay: 10
  2377.  
  2378. Start HW RxEn Seedless training
  2379.  
  2380. Chip Select: 03
  2381. Byte: 00 01 02 03 04 05 06 07 ECC
  2382. RxEn Orig: 066 068 069 06E 06F 072 077 07C
  2383. i: 00
  2384.  
  2385. j: 00
  2386. Byte: 00 01 02 03 04 05 06 07 ECC
  2387. Target BL Found: N N N N N N N N
  2388. Target BL Value: 000 000 000 000 000 000 000 000
  2389. Setting PassTestRxEnDly
  2390. PassTestRxEnDly: 076 078 079 07E 07F 082 087 08C
  2391. OutOfRange: N N N N N N N N
  2392. Checking if PassTestRxEnDly Passes?
  2393.  
  2394. MaxRdLat: 04E
  2395. TestAddr: 80200000
  2396. STAGE: 0 Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.
  2397.  
  2398. Byte Lane : 08 07 06 05 04 03 02 01 00
  2399. DQS Delays : 00 00 00 00 00 00 00 00 00
  2400. Result : P P P P P P P P P
  2401. ResultFound : Y
  2402.  
  2403. Byte Lane : 08 07 06 05 04 03 02 01 00
  2404. DQS Delays : 00 1C 1C 1C 1C 1C 1C 1C 1C
  2405. Result : . . . . . . . .
  2406. ResultFound : Y Y Y Y Y Y Y Y Y
  2407.  
  2408. STAGE: 1 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.
  2409.  
  2410. Byte Lane : 08 07 06 05 04 03 02 01 00
  2411. DQS Delays : 00 1D 1D 1D 1D 1D 1D 1D 1D
  2412. Result : P . . . . . . . .
  2413. ResultFound : Y
  2414.  
  2415. Byte Lane : 08 07 06 05 04 03 02 01 00
  2416. DQS Delays : 00 1E 1E 1E 1E 1E 1E 1E 1E
  2417. Result : . . . . . . . .
  2418. ResultFound : Y
  2419.  
  2420. Byte Lane : 08 07 06 05 04 03 02 01 00
  2421. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  2422. Result : P . . . . . P .
  2423. ResultFound : Y Y Y
  2424.  
  2425. Byte Lane : 08 07 06 05 04 03 02 01 00
  2426. DQS Delays : 00 1F 00 00 00 00 00 1F 00
  2427. Result : P P P P P P
  2428. ResultFound : Y Y Y Y Y Y Y Y Y
  2429.  
  2430. STAGE: 2 Sweeping Read DQS, decrementing from 1F by 04, until all bytelanes PASS.
  2431.  
  2432. Byte Lane : 08 07 06 05 04 03 02 01 00
  2433. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  2434. Result : P . . . . . . . .
  2435. ResultFound : Y
  2436.  
  2437. Byte Lane : 08 07 06 05 04 03 02 01 00
  2438. DQS Delays : 00 1B 1B 1B 1B 1B 1B 1B 1B
  2439. Result : . . . . . . . .
  2440. ResultFound : Y
  2441.  
  2442. Byte Lane : 08 07 06 05 04 03 02 01 00
  2443. DQS Delays : 00 17 17 17 17 17 17 17 17
  2444. Result : P P P P P P P P
  2445. ResultFound : Y Y Y Y Y Y Y Y Y
  2446.  
  2447. STAGE: 3 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.
  2448.  
  2449. Byte Lane : 08 07 06 05 04 03 02 01 00
  2450. DQS Delays : 00 18 18 18 18 18 18 18 18
  2451. Result : P P P P P P P P P
  2452. ResultFound : Y
  2453.  
  2454. Byte Lane : 08 07 06 05 04 03 02 01 00
  2455. DQS Delays : 00 19 19 19 19 19 19 19 19
  2456. Result : P P P P P P P P
  2457. ResultFound : Y
  2458.  
  2459. Byte Lane : 08 07 06 05 04 03 02 01 00
  2460. DQS Delays : 00 1A 1A 1A 1A 1A 1A 1A 1A
  2461. Result : . . P . P P P .
  2462. ResultFound : Y Y Y Y Y
  2463.  
  2464. Byte Lane : 08 07 06 05 04 03 02 01 00
  2465. DQS Delays : 00 1A 1A 1B 1A 1B 1B 1B 1A
  2466. Result : . . . .
  2467. ResultFound : Y Y Y Y Y Y Y Y Y
  2468.  
  2469. Data Eye Results:
  2470.  
  2471. Byte Left Right
  2472. Lane Edge Edge Width Center
  2473. 0 00 19 19 0D
  2474. 1 1F 1A 1B 0D
  2475. 2 00 1A 1A 0D
  2476. 3 00 1A 1A 0D
  2477. 4 00 19 19 0D
  2478. 5 00 1A 1A 0D
  2479. 6 00 19 19 0D
  2480. 7 1F 19 1A 0C
  2481.  
  2482. Byte: 00 01 02 03 04 05 06 07 ECC
  2483. Err Status: P P P P P P P P
  2484. Byte: 00 01 02 03 04 05 06 07 ECC
  2485. FailTestRxEnDly: 0B6 0B8 0B9 0BE 0BF 0C2 0C7 0CC
  2486. Setting FailTestRxEnDly
  2487. OutOfRange: N N N N N N N N
  2488. FailTestRxEnDly: Y Y Y Y Y Y Y Y
  2489.  
  2490. Checking if FailTestRxEnDly Fails?
  2491. MaxRdLat: 054
  2492. TestAddr: 80200000
  2493. STAGE: 0 Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.
  2494.  
  2495. Byte Lane : 08 07 06 05 04 03 02 01 00
  2496. DQS Delays : 00 00 00 00 00 00 00 00 00
  2497. Result : P . . . . . . . .
  2498. ResultFound : Y Y Y Y Y Y Y Y Y
  2499.  
  2500. STAGE: 1 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.
  2501.  
  2502. Byte Lane : 08 07 06 05 04 03 02 01 00
  2503. DQS Delays : 00 01 01 01 01 01 01 01 01
  2504. Result : P . . . . . . . .
  2505. ResultFound : Y
  2506.  
  2507. Byte Lane : 08 07 06 05 04 03 02 01 00
  2508. DQS Delays : 00 02 02 02 02 02 02 02 02
  2509. Result : . . . . . . . .
  2510. ResultFound : Y
  2511.  
  2512. Byte Lane : 08 07 06 05 04 03 02 01 00
  2513. DQS Delays : 00 03 03 03 03 03 03 03 03
  2514. Result : . . . . . . . .
  2515. ResultFound : Y
  2516.  
  2517. Byte Lane : 08 07 06 05 04 03 02 01 00
  2518. DQS Delays : 00 04 04 04 04 04 04 04 04
  2519. Result : . . . . . . . .
  2520. ResultFound : Y
  2521.  
  2522. Byte Lane : 08 07 06 05 04 03 02 01 00
  2523. DQS Delays : 00 05 05 05 05 05 05 05 05
  2524. Result : . . . . . . . .
  2525. ResultFound : Y
  2526.  
  2527. Byte Lane : 08 07 06 05 04 03 02 01 00
  2528. DQS Delays : 00 06 06 06 06 06 06 06 06
  2529. Result : . . . . . . . .
  2530. ResultFound : Y
  2531.  
  2532. Byte Lane : 08 07 06 05 04 03 02 01 00
  2533. DQS Delays : 00 07 07 07 07 07 07 07 07
  2534. Result : . . . . . . . .
  2535. ResultFound : Y
  2536.  
  2537. Byte Lane : 08 07 06 05 04 03 02 01 00
  2538. DQS Delays : 00 08 08 08 08 08 08 08 08
  2539. Result : . . . . . . . .
  2540. ResultFound : Y
  2541.  
  2542. Byte Lane : 08 07 06 05 04 03 02 01 00
  2543. DQS Delays : 00 09 09 09 09 09 09 09 09
  2544. Result : . . . . . . . .
  2545. ResultFound : Y
  2546.  
  2547. Byte Lane : 08 07 06 05 04 03 02 01 00
  2548. DQS Delays : 00 0A 0A 0A 0A 0A 0A 0A 0A
  2549. Result : . . . . . . . .
  2550. ResultFound : Y
  2551.  
  2552. Byte Lane : 08 07 06 05 04 03 02 01 00
  2553. DQS Delays : 00 0B 0B 0B 0B 0B 0B 0B 0B
  2554. Result : . . . . . . . .
  2555. ResultFound : Y
  2556.  
  2557. Byte Lane : 08 07 06 05 04 03 02 01 00
  2558. DQS Delays : 00 0C 0C 0C 0C 0C 0C 0C 0C
  2559. Result : . . . . . . . .
  2560. ResultFound : Y
  2561.  
  2562. Byte Lane : 08 07 06 05 04 03 02 01 00
  2563. DQS Delays : 00 0D 0D 0D 0D 0D 0D 0D 0D
  2564. Result : . . . . . . . .
  2565. ResultFound : Y
  2566.  
  2567. Byte Lane : 08 07 06 05 04 03 02 01 00
  2568. DQS Delays : 00 0E 0E 0E 0E 0E 0E 0E 0E
  2569. Result : . . . . . . . .
  2570. ResultFound : Y
  2571.  
  2572. Byte Lane : 08 07 06 05 04 03 02 01 00
  2573. DQS Delays : 00 0F 0F 0F 0F 0F 0F 0F 0F
  2574. Result : . . . . . . . .
  2575. ResultFound : Y
  2576.  
  2577. Byte Lane : 08 07 06 05 04 03 02 01 00
  2578. DQS Delays : 00 10 10 10 10 10 10 10 10
  2579. Result : . . . . . . . .
  2580. ResultFound : Y
  2581.  
  2582. Byte Lane : 08 07 06 05 04 03 02 01 00
  2583. DQS Delays : 00 11 11 11 11 11 11 11 11
  2584. Result : . . . . . . . .
  2585. ResultFound : Y
  2586.  
  2587. Byte Lane : 08 07 06 05 04 03 02 01 00
  2588. DQS Delays : 00 12 12 12 12 12 12 12 12
  2589. Result : . . . . . . . .
  2590. ResultFound : Y
  2591.  
  2592. Byte Lane : 08 07 06 05 04 03 02 01 00
  2593. DQS Delays : 00 13 13 13 13 13 13 13 13
  2594. Result : . . . . . . . .
  2595. ResultFound : Y
  2596.  
  2597. Byte Lane : 08 07 06 05 04 03 02 01 00
  2598. DQS Delays : 00 14 14 14 14 14 14 14 14
  2599. Result : . . . . . . . .
  2600. ResultFound : Y
  2601.  
  2602. Byte Lane : 08 07 06 05 04 03 02 01 00
  2603. DQS Delays : 00 15 15 15 15 15 15 15 15
  2604. Result : . . . . . . . .
  2605. ResultFound : Y
  2606.  
  2607. Byte Lane : 08 07 06 05 04 03 02 01 00
  2608. DQS Delays : 00 16 16 16 16 16 16 16 16
  2609. Result : . . . . . . . .
  2610. ResultFound : Y
  2611.  
  2612. Byte Lane : 08 07 06 05 04 03 02 01 00
  2613. DQS Delays : 00 17 17 17 17 17 17 17 17
  2614. Result : . . . . . . . .
  2615. ResultFound : Y
  2616.  
  2617. Byte Lane : 08 07 06 05 04 03 02 01 00
  2618. DQS Delays : 00 18 18 18 18 18 18 18 18
  2619. Result : . . . . . . . .
  2620. ResultFound : Y
  2621.  
  2622. Byte Lane : 08 07 06 05 04 03 02 01 00
  2623. DQS Delays : 00 19 19 19 19 19 19 19 19
  2624. Result : . . . . . . . .
  2625. ResultFound : Y
  2626.  
  2627. Byte Lane : 08 07 06 05 04 03 02 01 00
  2628. DQS Delays : 00 1A 1A 1A 1A 1A 1A 1A 1A
  2629. Result : . . . . . . . .
  2630. ResultFound : Y
  2631.  
  2632. Byte Lane : 08 07 06 05 04 03 02 01 00
  2633. DQS Delays : 00 1B 1B 1B 1B 1B 1B 1B 1B
  2634. Result : . . . . . . . .
  2635. ResultFound : Y
  2636.  
  2637. Byte Lane : 08 07 06 05 04 03 02 01 00
  2638. DQS Delays : 00 1C 1C 1C 1C 1C 1C 1C 1C
  2639. Result : . . . . . . . .
  2640. ResultFound : Y
  2641.  
  2642. Byte Lane : 08 07 06 05 04 03 02 01 00
  2643. DQS Delays : 00 1D 1D 1D 1D 1D 1D 1D 1D
  2644. Result : . . . . . . . .
  2645. ResultFound : Y
  2646.  
  2647. Byte Lane : 08 07 06 05 04 03 02 01 00
  2648. DQS Delays : 00 1E 1E 1E 1E 1E 1E 1E 1E
  2649. Result : . . . . . . . .
  2650. ResultFound : Y
  2651.  
  2652. Byte Lane : 08 07 06 05 04 03 02 01 00
  2653. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  2654. Result : . . . . . . . .
  2655. ResultFound : Y
  2656.  
  2657. --DATA EYE NOT FOUND--
  2658.  
  2659.  
  2660. Byte: 00 01 02 03 04 05 06 07 ECC
  2661. Err Status: F F F F F F F F
  2662. Set FinalRxEnCycle: Y Y Y Y Y Y Y Y
  2663. OutOfRange: N N N N N N N N
  2664. FinalRxEnCycle: 066 068 069 06E 06F 072 077 07C
  2665. ByteLaneFail: Y Y Y Y Y Y Y Y
  2666. ByteLanePass: Y Y Y Y Y Y Y Y
  2667.  
  2668. Setting new RDQS based on FinalRxEnCycle
  2669.  
  2670. MaxRdLat: 04E
  2671. TestAddr: 80200000
  2672. STAGE: 0 Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.
  2673.  
  2674. Byte Lane : 08 07 06 05 04 03 02 01 00
  2675. DQS Delays : 00 00 00 00 00 00 00 00 00
  2676. Result : P P P P P P P P P
  2677. ResultFound : Y
  2678.  
  2679. Byte Lane : 08 07 06 05 04 03 02 01 00
  2680. DQS Delays : 00 1C 1C 1C 1C 1C 1C 1C 1C
  2681. Result : . . . . . . . .
  2682. ResultFound : Y Y Y Y Y Y Y Y Y
  2683.  
  2684. STAGE: 1 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.
  2685.  
  2686. Byte Lane : 08 07 06 05 04 03 02 01 00
  2687. DQS Delays : 00 1D 1D 1D 1D 1D 1D 1D 1D
  2688. Result : P . . . . . . . .
  2689. ResultFound : Y
  2690.  
  2691. Byte Lane : 08 07 06 05 04 03 02 01 00
  2692. DQS Delays : 00 1E 1E 1E 1E 1E 1E 1E 1E
  2693. Result : . . . . . . . .
  2694. ResultFound : Y
  2695.  
  2696. Byte Lane : 08 07 06 05 04 03 02 01 00
  2697. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  2698. Result : P . . . P . P P
  2699. ResultFound : Y Y Y Y Y
  2700.  
  2701. Byte Lane : 08 07 06 05 04 03 02 01 00
  2702. DQS Delays : 00 1F 00 00 00 1F 00 1F 1F
  2703. Result : P P P P
  2704. ResultFound : Y Y Y Y Y Y Y Y Y
  2705.  
  2706. STAGE: 2 Sweeping Read DQS, decrementing from 1F by 04, until all bytelanes PASS.
  2707.  
  2708. Byte Lane : 08 07 06 05 04 03 02 01 00
  2709. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  2710. Result : P . . . . . . . .
  2711. ResultFound : Y
  2712.  
  2713. Byte Lane : 08 07 06 05 04 03 02 01 00
  2714. DQS Delays : 00 1B 1B 1B 1B 1B 1B 1B 1B
  2715. Result : . . . . . . . .
  2716. ResultFound : Y
  2717.  
  2718. Byte Lane : 08 07 06 05 04 03 02 01 00
  2719. DQS Delays : 00 17 17 17 17 17 17 17 17
  2720. Result : P P P P P P P P
  2721. ResultFound : Y Y Y Y Y Y Y Y Y
  2722.  
  2723. STAGE: 3 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.
  2724.  
  2725. Byte Lane : 08 07 06 05 04 03 02 01 00
  2726. DQS Delays : 00 18 18 18 18 18 18 18 18
  2727. Result : P P P P P P P P P
  2728. ResultFound : Y
  2729.  
  2730. Byte Lane : 08 07 06 05 04 03 02 01 00
  2731. DQS Delays : 00 19 19 19 19 19 19 19 19
  2732. Result : P P P P P P P P
  2733. ResultFound : Y
  2734.  
  2735. Byte Lane : 08 07 06 05 04 03 02 01 00
  2736. DQS Delays : 00 1A 1A 1A 1A 1A 1A 1A 1A
  2737. Result : . . P . P . P .
  2738. ResultFound : Y Y Y Y Y Y
  2739.  
  2740. Byte Lane : 08 07 06 05 04 03 02 01 00
  2741. DQS Delays : 00 1A 1A 1B 1A 1B 1A 1B 1A
  2742. Result : . . .
  2743. ResultFound : Y Y Y Y Y Y Y Y Y
  2744.  
  2745. Data Eye Results:
  2746.  
  2747. Byte Left Right
  2748. Lane Edge Edge Width Center
  2749. 0 1F 19 1A 0C
  2750. 1 1F 1A 1B 0D
  2751. 2 00 19 19 0D
  2752. 3 1F 1A 1B 0D
  2753. 4 00 19 19 0D
  2754. 5 00 1A 1A 0D
  2755. 6 00 19 19 0D
  2756. 7 1F 19 1A 0C
  2757.  
  2758.  
  2759. End HW RxEn Seedless training
  2760.  
  2761.  
  2762. Train WrDat:
  2763.  
  2764. STAGE: 0 Sweeping Write DQS, incrementing from 00 by 04, until all bytelanes PASS.
  2765.  
  2766. Byte Lane : 08 07 06 05 04 03 02 01 00
  2767. DQS Delays : 00 00 00 00 00 00 00 00 00
  2768. Result : P . . . . . . . .
  2769. ResultFound : Y
  2770.  
  2771. Byte Lane : 08 07 06 05 04 03 02 01 00
  2772. DQS Delays : 00 04 04 04 04 04 04 04 04
  2773. Result : P P P P P P P P
  2774. ResultFound : Y Y Y Y Y Y Y Y Y
  2775.  
  2776. STAGE: 1 Sweeping Write DQS, decrementing from Current Delay by 01, until all bytelanes FAIL.
  2777.  
  2778. Byte Lane : 08 07 06 05 04 03 02 01 00
  2779. DQS Delays : 00 03 03 03 03 03 03 03 03
  2780. Result : P P P P P P P P P
  2781. ResultFound : Y
  2782.  
  2783. Byte Lane : 08 07 06 05 04 03 02 01 00
  2784. DQS Delays : 00 02 02 02 02 02 02 02 02
  2785. Result : . . P P P P P P
  2786. ResultFound : Y Y Y
  2787.  
  2788. Byte Lane : 08 07 06 05 04 03 02 01 00
  2789. DQS Delays : 00 02 02 01 01 01 01 01 01
  2790. Result : . . . P . .
  2791. ResultFound : Y Y Y Y Y Y Y Y
  2792.  
  2793. Byte Lane : 08 07 06 05 04 03 02 01 00
  2794. DQS Delays : 00 02 02 01 01 01 00 01 01
  2795. Result : .
  2796. ResultFound : Y Y Y Y Y Y Y Y Y
  2797.  
  2798. STAGE: 2 Sweeping Write DQS, decrementing from 1F by 04, until all bytelanes PASS.
  2799.  
  2800. Byte Lane : 08 07 06 05 04 03 02 01 00
  2801. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  2802. Result : P . . . . . . . .
  2803. ResultFound : Y
  2804.  
  2805. Byte Lane : 08 07 06 05 04 03 02 01 00
  2806. DQS Delays : 00 1B 1B 1B 1B 1B 1B 1B 1B
  2807. Result : P P P P P P P P
  2808. ResultFound : Y Y Y Y Y Y Y Y Y
  2809.  
  2810. STAGE: 3 Sweeping Write DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.
  2811.  
  2812. Byte Lane : 08 07 06 05 04 03 02 01 00
  2813. DQS Delays : 00 1C 1C 1C 1C 1C 1C 1C 1C
  2814. Result : P P P P P P P P P
  2815. ResultFound : Y
  2816.  
  2817. Byte Lane : 08 07 06 05 04 03 02 01 00
  2818. DQS Delays : 00 1D 1D 1D 1D 1D 1D 1D 1D
  2819. Result : P P P P P P P P
  2820. ResultFound : Y
  2821.  
  2822. Byte Lane : 08 07 06 05 04 03 02 01 00
  2823. DQS Delays : 00 1E 1E 1E 1E 1E 1E 1E 1E
  2824. Result : P P P . . P P P
  2825. ResultFound : Y Y Y
  2826.  
  2827. Byte Lane : 08 07 06 05 04 03 02 01 00
  2828. DQS Delays : 00 1F 1F 1F 1E 1E 1F 1F 1F
  2829. Result : . . . . . .
  2830. ResultFound : Y Y Y Y Y Y Y Y Y
  2831.  
  2832. Data Eye Results:
  2833.  
  2834. Byte Left Right
  2835. Lane Edge Edge Width Center
  2836. 0 02 1E 1C 10
  2837. 1 02 1E 1C 10
  2838. 2 01 1E 1D 10
  2839. 3 02 1D 1B 10
  2840. 4 02 1D 1B 10
  2841. 5 02 1E 1C 10
  2842. 6 03 1E 1B 11
  2843. 7 03 1E 1B 11
  2844. End Read/Write Data Eye Edge Detection
  2845.  
  2846. MemFInitTableDrive [000000000000000E] Start
  2847. MemFInitTableDrive End
  2848.  
  2849. Load Training registers for M1 with DDR667 training result
  2850. LD: 1 ROD: 0 WOD: 0 WrEarlyx2: 0
  2851.  
  2852. TrdrdSdSc : 01
  2853. CDDTrdrdSdDc : 00 TrdrdSdDc : 03
  2854. CDDTrdrdDd : FFFFFF81 TrdrdDd : 03
  2855.  
  2856. TwrwrSdSc : 01
  2857. CDDTwrwrSdDc : 00 TwrwrSdDc : 04
  2858. CDDTwrwrDd : FFFFFF81 TwrwrDd : 04
  2859.  
  2860. TrwtWB : 06
  2861. CDDTwrrd : FD Twrrd : 02
  2862. CDDTrwtTO : 03 TrwtTO : 05
  2863.  
  2864. MemFInitTableDrive [0000000000000005] Start
  2865. MemFInitTableDrive End
  2866.  
  2867. Going into training stage 2. Complete training at DDR667 is done.
  2868.  
  2869. MemClkFreq changed: 333 MHz -> 667 MHzMemFInitTableDrive [0000000000000001] Start
  2870. MemFInitTableDrive End
  2871. MemFInitTableDrive [0000000000000002] Start
  2872. MemFInitTableDrive End
  2873. Memclk Freq: 667
  2874. RdPtr: 6
  2875. MemFInitTableDrive [0000000000000010] Start
  2876. MemFInitTableDrive End
  2877. Dct 1
  2878. FenceThresholdTxDll
  2879. Seeds: 13 13 13 13 13 13 13 13 13
  2880. PhyFenceTrEn = 1
  2881. PRE: 1A 1A 1A 19 19 1A 1A 19 1A
  2882. Fence: 12
  2883.  
  2884. FenceThresholdRxDll
  2885. Seeds: 13 13 13 13 13 13 13 13 13
  2886. PhyFenceTrEn = 1
  2887. PRE: 18 18 18 18 18 1A 19 19 18
  2888. Fence: 11
  2889.  
  2890. FenceThresholdTxPad
  2891. Seeds: 13 13 13 13 13 13 13 13 13
  2892. PhyFenceTrEn = 1
  2893. PRE: 19 19 19 19 19 19 19 19 19
  2894. Fence: 11
  2895. Dct 0
  2896. Dct 1
  2897. CS2 MR2 00090
  2898. CS2 MR3 00000
  2899. CS2 MR1 00006
  2900. CS2 MR0 01B59
  2901. CS3 MR2 00090 swapped to -> CS3 MR1 00108
  2902. CS3 MR3 00000 swapped to -> CS3 MR3 00000
  2903. CS3 MR1 00006 swapped to -> CS3 MR2 00006
  2904. CS3 MR0 01B59 swapped to -> CS3 MR0 01AB9
  2905. MemFInitTableDrive [000000000000000A] Start
  2906. MemFInitTableDrive End
  2907.  
  2908. Start write leveling
  2909. Dct 0
  2910. Dct 1
  2911. CS 2
  2912. CS2 MR1 00086
  2913. CS2 MR2 00090
  2914. CS3 MR1 01086 swapped to -> CS3 MR2 01106
  2915. CS3 MR2 00090 swapped to -> CS3 MR1 00108
  2916.  
  2917. Byte: 00 01 02 03 04 05 06 07 ECC
  2918. Seeds: 50 56 5E 24 2E 34 38 3A 2A
  2919. WrtLvTrEn = 1
  2920. PRE: 4F 59 62 25 2E 37 3A 3B
  2921. WrDqs: 0F 19 22 25 2E 37 3A 3B
  2922.  
  2923. CS2 MR1 00006
  2924. CS2 MR2 00090
  2925. CS3 MR1 00006 swapped to -> CS3 MR2 00006
  2926. CS3 MR2 00090 swapped to -> CS3 MR1 00108
  2927. CS 3
  2928. CS2 MR1 01086
  2929. CS2 MR2 00090
  2930. CS3 MR1 00086 swapped to -> CS3 MR2 00106
  2931. CS3 MR2 00090 swapped to -> CS3 MR1 00108
  2932.  
  2933. Byte: 00 01 02 03 04 05 06 07 ECC
  2934. Seeds: 50 5A 22 26 30 38 3C 3E 2A
  2935. WrtLvTrEn = 1
  2936. PRE: 52 5B 22 27 30 39 3E 3F
  2937. WrDqs: 12 1B 22 27 30 39 3E 3F
  2938.  
  2939. CS2 MR1 00006
  2940. CS2 MR2 00090
  2941. CS3 MR1 00006 swapped to -> CS3 MR2 00006
  2942. CS3 MR2 00090 swapped to -> CS3 MR1 00108
  2943. End write leveling
  2944.  
  2945. MemFInitTableDrive [000000000000000B] Start
  2946. MemFInitTableDrive End
  2947.  
  2948. Start HW RxEn training
  2949. Dct 0
  2950. Dct 1
  2951. CS 2
  2952. TestAddr 200000
  2953. Byte: 00 01 02 03 04 05 06 07 ECC
  2954. SeedTotal: 08A 08E 092 098 09E 0A2 0AC 0B6
  2955. SeedPRE: 04A 04E 052 058 05E 022 02C 036
  2956. PRE: 045 048 04D 053 057 01E 027 02F
  2957. RxEn: 0A5 0A8 0AD 0B3 0B7 0BE 0C7 0CF
  2958.  
  2959. CS 3
  2960. TestAddr 80200000
  2961. Byte: 00 01 02 03 04 05 06 07 ECC
  2962. SeedTotal: 08C 090 092 09C 09E 0A4 0AE 0B8
  2963. SeedPRE: 04C 050 052 05C 05E 024 02E 038
  2964. PRE: 048 04B 04D 057 058 020 028 032
  2965. RxEn: 0A8 0AB 0AD 0B7 0B8 0C0 0C8 0D2
  2966.  
  2967. End HW RxEn training
  2968.  
  2969. MemFInitTableDrive [000000000000000C] Start
  2970. MemFInitTableDrive End
  2971. Dct 0
  2972. Dct 1
  2973. MaxRdLat: 033
  2974. MemFInitTableDrive [000000000000000D] Start
  2975. MemFInitTableDrive End
  2976.  
  2977. Start Read/Write Data Eye Edge Detection.
  2978. Dct 0
  2979. Dct 1
  2980. CS 2
  2981. Increase WrDat, Train RdDqs:
  2982.  
  2983. Write Delay: 10
  2984.  
  2985. Start HW RxEn Seedless training
  2986.  
  2987. Chip Select: 02
  2988. Byte: 00 01 02 03 04 05 06 07 ECC
  2989. RxEn Orig: 0A5 0A8 0AD 0B3 0B7 0BE 0C7 0CF
  2990. i: 00
  2991.  
  2992. j: 00
  2993. Byte: 00 01 02 03 04 05 06 07 ECC
  2994. Target BL Found: N N N N N N N N
  2995. Target BL Value: 000 000 000 000 000 000 000 000
  2996. Setting PassTestRxEnDly
  2997. PassTestRxEnDly: 0B5 0B8 0BD 0C3 0C7 0CE 0D7 0DF
  2998. OutOfRange: N N N N N N N N
  2999. Checking if PassTestRxEnDly Passes?
  3000.  
  3001. MaxRdLat: 034
  3002. TestAddr: 200000
  3003. STAGE: 0 Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.
  3004.  
  3005. Byte Lane : 08 07 06 05 04 03 02 01 00
  3006. DQS Delays : 00 00 00 00 00 00 00 00 00
  3007. Result : P P P P P P P P P
  3008. ResultFound : Y
  3009.  
  3010. Byte Lane : 08 07 06 05 04 03 02 01 00
  3011. DQS Delays : 00 1C 1C 1C 1C 1C 1C 1C 1C
  3012. Result : . . . . . . . .
  3013. ResultFound : Y Y Y Y Y Y Y Y Y
  3014.  
  3015. STAGE: 1 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.
  3016.  
  3017. Byte Lane : 08 07 06 05 04 03 02 01 00
  3018. DQS Delays : 00 1D 1D 1D 1D 1D 1D 1D 1D
  3019. Result : P . . . P . . . .
  3020. ResultFound : Y Y
  3021.  
  3022. Byte Lane : 08 07 06 05 04 03 02 01 00
  3023. DQS Delays : 00 1E 1E 1E 1D 1E 1E 1E 1E
  3024. Result : . P . . P . .
  3025. ResultFound : Y Y Y Y
  3026.  
  3027. Byte Lane : 08 07 06 05 04 03 02 01 00
  3028. DQS Delays : 00 1F 1E 1F 1D 1F 1E 1F 1F
  3029. Result : P P P P P
  3030. ResultFound : Y Y Y Y Y Y Y Y Y
  3031.  
  3032. STAGE: 2 Sweeping Read DQS, decrementing from 1F by 04, until all bytelanes PASS.
  3033.  
  3034. Byte Lane : 08 07 06 05 04 03 02 01 00
  3035. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  3036. Result : P . . . . . . . .
  3037. ResultFound : Y
  3038.  
  3039. Byte Lane : 08 07 06 05 04 03 02 01 00
  3040. DQS Delays : 00 1B 1B 1B 1B 1B 1B 1B 1B
  3041. Result : . . . . . . . .
  3042. ResultFound : Y
  3043.  
  3044. Byte Lane : 08 07 06 05 04 03 02 01 00
  3045. DQS Delays : 00 17 17 17 17 17 17 17 17
  3046. Result : . P . . . . . P
  3047. ResultFound : Y Y Y
  3048.  
  3049. Byte Lane : 08 07 06 05 04 03 02 01 00
  3050. DQS Delays : 00 13 17 13 13 13 13 13 17
  3051. Result : P P P P P P
  3052. ResultFound : Y Y Y Y Y Y Y Y Y
  3053.  
  3054. STAGE: 3 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.
  3055.  
  3056. Byte Lane : 08 07 06 05 04 03 02 01 00
  3057. DQS Delays : 00 14 18 14 14 14 14 14 18
  3058. Result : P P . P P P P P .
  3059. ResultFound : Y Y Y
  3060.  
  3061. Byte Lane : 08 07 06 05 04 03 02 01 00
  3062. DQS Delays : 00 15 18 15 15 15 15 15 18
  3063. Result : P P P P P P
  3064. ResultFound : Y Y Y
  3065.  
  3066. Byte Lane : 08 07 06 05 04 03 02 01 00
  3067. DQS Delays : 00 16 18 16 16 16 16 16 18
  3068. Result : . . P . P .
  3069. ResultFound : Y Y Y Y Y Y Y
  3070.  
  3071. Byte Lane : 08 07 06 05 04 03 02 01 00
  3072. DQS Delays : 00 16 18 16 17 16 17 16 18
  3073. Result : . .
  3074. ResultFound : Y Y Y Y Y Y Y Y Y
  3075.  
  3076. Data Eye Results:
  3077.  
  3078. Byte Left Right
  3079. Lane Edge Edge Width Center
  3080. 0 1F 17 18 0B
  3081. 1 1F 15 16 0A
  3082. 2 1E 16 18 0A
  3083. 3 1F 15 16 0A
  3084. 4 1D 16 19 0A
  3085. 5 1F 15 16 0A
  3086. 6 1E 17 19 0B
  3087. 7 1F 15 16 0A
  3088.  
  3089. Byte: 00 01 02 03 04 05 06 07 ECC
  3090. Err Status: P P P P P P P P
  3091. Byte: 00 01 02 03 04 05 06 07 ECC
  3092. FailTestRxEnDly: 0F5 0F8 0FD 103 107 10E 117 11F
  3093. Setting FailTestRxEnDly
  3094. OutOfRange: N N N N N N N N
  3095. FailTestRxEnDly: Y Y Y Y Y Y Y Y
  3096.  
  3097. Checking if FailTestRxEnDly Fails?
  3098. MaxRdLat: 037
  3099. TestAddr: 200000
  3100. STAGE: 0 Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.
  3101.  
  3102. Byte Lane : 08 07 06 05 04 03 02 01 00
  3103. DQS Delays : 00 00 00 00 00 00 00 00 00
  3104. Result : P . . . . . . . .
  3105. ResultFound : Y Y Y Y Y Y Y Y Y
  3106.  
  3107. STAGE: 1 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.
  3108.  
  3109. Byte Lane : 08 07 06 05 04 03 02 01 00
  3110. DQS Delays : 00 01 01 01 01 01 01 01 01
  3111. Result : P . . . . . . . .
  3112. ResultFound : Y
  3113.  
  3114. Byte Lane : 08 07 06 05 04 03 02 01 00
  3115. DQS Delays : 00 02 02 02 02 02 02 02 02
  3116. Result : . . . . . . . .
  3117. ResultFound : Y
  3118.  
  3119. Byte Lane : 08 07 06 05 04 03 02 01 00
  3120. DQS Delays : 00 03 03 03 03 03 03 03 03
  3121. Result : . . . . . . . .
  3122. ResultFound : Y
  3123.  
  3124. Byte Lane : 08 07 06 05 04 03 02 01 00
  3125. DQS Delays : 00 04 04 04 04 04 04 04 04
  3126. Result : . . . . . . . .
  3127. ResultFound : Y
  3128.  
  3129. Byte Lane : 08 07 06 05 04 03 02 01 00
  3130. DQS Delays : 00 05 05 05 05 05 05 05 05
  3131. Result : . . . . . . . .
  3132. ResultFound : Y
  3133.  
  3134. Byte Lane : 08 07 06 05 04 03 02 01 00
  3135. DQS Delays : 00 06 06 06 06 06 06 06 06
  3136. Result : . . . . . . . .
  3137. ResultFound : Y
  3138.  
  3139. Byte Lane : 08 07 06 05 04 03 02 01 00
  3140. DQS Delays : 00 07 07 07 07 07 07 07 07
  3141. Result : . . . . . . . .
  3142. ResultFound : Y
  3143.  
  3144. Byte Lane : 08 07 06 05 04 03 02 01 00
  3145. DQS Delays : 00 08 08 08 08 08 08 08 08
  3146. Result : . . . . . . . .
  3147. ResultFound : Y
  3148.  
  3149. Byte Lane : 08 07 06 05 04 03 02 01 00
  3150. DQS Delays : 00 09 09 09 09 09 09 09 09
  3151. Result : . . . . . . . .
  3152. ResultFound : Y
  3153.  
  3154. Byte Lane : 08 07 06 05 04 03 02 01 00
  3155. DQS Delays : 00 0A 0A 0A 0A 0A 0A 0A 0A
  3156. Result : . . . . . . . .
  3157. ResultFound : Y
  3158.  
  3159. Byte Lane : 08 07 06 05 04 03 02 01 00
  3160. DQS Delays : 00 0B 0B 0B 0B 0B 0B 0B 0B
  3161. Result : . . . . . . . .
  3162. ResultFound : Y
  3163.  
  3164. Byte Lane : 08 07 06 05 04 03 02 01 00
  3165. DQS Delays : 00 0C 0C 0C 0C 0C 0C 0C 0C
  3166. Result : . . . . . . . .
  3167. ResultFound : Y
  3168.  
  3169. Byte Lane : 08 07 06 05 04 03 02 01 00
  3170. DQS Delays : 00 0D 0D 0D 0D 0D 0D 0D 0D
  3171. Result : . . . . . . . .
  3172. ResultFound : Y
  3173.  
  3174. Byte Lane : 08 07 06 05 04 03 02 01 00
  3175. DQS Delays : 00 0E 0E 0E 0E 0E 0E 0E 0E
  3176. Result : . . . . . . . .
  3177. ResultFound : Y
  3178.  
  3179. Byte Lane : 08 07 06 05 04 03 02 01 00
  3180. DQS Delays : 00 0F 0F 0F 0F 0F 0F 0F 0F
  3181. Result : . . . . . . . .
  3182. ResultFound : Y
  3183.  
  3184. Byte Lane : 08 07 06 05 04 03 02 01 00
  3185. DQS Delays : 00 10 10 10 10 10 10 10 10
  3186. Result : . . . . . . . .
  3187. ResultFound : Y
  3188.  
  3189. Byte Lane : 08 07 06 05 04 03 02 01 00
  3190. DQS Delays : 00 11 11 11 11 11 11 11 11
  3191. Result : . . . . . . . .
  3192. ResultFound : Y
  3193.  
  3194. Byte Lane : 08 07 06 05 04 03 02 01 00
  3195. DQS Delays : 00 12 12 12 12 12 12 12 12
  3196. Result : . . . . . . . .
  3197. ResultFound : Y
  3198.  
  3199. Byte Lane : 08 07 06 05 04 03 02 01 00
  3200. DQS Delays : 00 13 13 13 13 13 13 13 13
  3201. Result : . . . . . . . .
  3202. ResultFound : Y
  3203.  
  3204. Byte Lane : 08 07 06 05 04 03 02 01 00
  3205. DQS Delays : 00 14 14 14 14 14 14 14 14
  3206. Result : . . . . . . . .
  3207. ResultFound : Y
  3208.  
  3209. Byte Lane : 08 07 06 05 04 03 02 01 00
  3210. DQS Delays : 00 15 15 15 15 15 15 15 15
  3211. Result : . . . . . . . .
  3212. ResultFound : Y
  3213.  
  3214. Byte Lane : 08 07 06 05 04 03 02 01 00
  3215. DQS Delays : 00 16 16 16 16 16 16 16 16
  3216. Result : . . . . . . . .
  3217. ResultFound : Y
  3218.  
  3219. Byte Lane : 08 07 06 05 04 03 02 01 00
  3220. DQS Delays : 00 17 17 17 17 17 17 17 17
  3221. Result : . . . . . . . .
  3222. ResultFound : Y
  3223.  
  3224. Byte Lane : 08 07 06 05 04 03 02 01 00
  3225. DQS Delays : 00 18 18 18 18 18 18 18 18
  3226. Result : . . . . . . . .
  3227. ResultFound : Y
  3228.  
  3229. Byte Lane : 08 07 06 05 04 03 02 01 00
  3230. DQS Delays : 00 19 19 19 19 19 19 19 19
  3231. Result : . . . . . . . .
  3232. ResultFound : Y
  3233.  
  3234. Byte Lane : 08 07 06 05 04 03 02 01 00
  3235. DQS Delays : 00 1A 1A 1A 1A 1A 1A 1A 1A
  3236. Result : . . . . . . . .
  3237. ResultFound : Y
  3238.  
  3239. Byte Lane : 08 07 06 05 04 03 02 01 00
  3240. DQS Delays : 00 1B 1B 1B 1B 1B 1B 1B 1B
  3241. Result : . . . . . . . .
  3242. ResultFound : Y
  3243.  
  3244. Byte Lane : 08 07 06 05 04 03 02 01 00
  3245. DQS Delays : 00 1C 1C 1C 1C 1C 1C 1C 1C
  3246. Result : . . . . . . . .
  3247. ResultFound : Y
  3248.  
  3249. Byte Lane : 08 07 06 05 04 03 02 01 00
  3250. DQS Delays : 00 1D 1D 1D 1D 1D 1D 1D 1D
  3251. Result : . . . . . . . .
  3252. ResultFound : Y
  3253.  
  3254. Byte Lane : 08 07 06 05 04 03 02 01 00
  3255. DQS Delays : 00 1E 1E 1E 1E 1E 1E 1E 1E
  3256. Result : . . . . . . . .
  3257. ResultFound : Y
  3258.  
  3259. Byte Lane : 08 07 06 05 04 03 02 01 00
  3260. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  3261. Result : . . . . . . . .
  3262. ResultFound : Y
  3263.  
  3264. --DATA EYE NOT FOUND--
  3265.  
  3266.  
  3267. Byte: 00 01 02 03 04 05 06 07 ECC
  3268. Err Status: F F F F F F F F
  3269. Set FinalRxEnCycle: Y Y Y Y Y Y Y Y
  3270. OutOfRange: N N N N N N N N
  3271. FinalRxEnCycle: 0A5 0A8 0AD 0B3 0B7 0BE 0C7 0CF
  3272. ByteLaneFail: Y Y Y Y Y Y Y Y
  3273. ByteLanePass: Y Y Y Y Y Y Y Y
  3274.  
  3275. Setting new RDQS based on FinalRxEnCycle
  3276.  
  3277. MaxRdLat: 033
  3278. TestAddr: 200000
  3279. STAGE: 0 Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.
  3280.  
  3281. Byte Lane : 08 07 06 05 04 03 02 01 00
  3282. DQS Delays : 00 00 00 00 00 00 00 00 00
  3283. Result : P P P P P P P P P
  3284. ResultFound : Y
  3285.  
  3286. Byte Lane : 08 07 06 05 04 03 02 01 00
  3287. DQS Delays : 00 1C 1C 1C 1C 1C 1C 1C 1C
  3288. Result : . . . . . . . .
  3289. ResultFound : Y Y Y Y Y Y Y Y Y
  3290.  
  3291. STAGE: 1 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.
  3292.  
  3293. Byte Lane : 08 07 06 05 04 03 02 01 00
  3294. DQS Delays : 00 1D 1D 1D 1D 1D 1D 1D 1D
  3295. Result : P . . . P . . . .
  3296. ResultFound : Y Y
  3297.  
  3298. Byte Lane : 08 07 06 05 04 03 02 01 00
  3299. DQS Delays : 00 1E 1E 1E 1D 1E 1E 1E 1E
  3300. Result : . P P P . . .
  3301. ResultFound : Y Y Y Y Y
  3302.  
  3303. Byte Lane : 08 07 06 05 04 03 02 01 00
  3304. DQS Delays : 00 1F 1E 1E 1D 1E 1F 1F 1F
  3305. Result : P P P P
  3306. ResultFound : Y Y Y Y Y Y Y Y Y
  3307.  
  3308. STAGE: 2 Sweeping Read DQS, decrementing from 1F by 04, until all bytelanes PASS.
  3309.  
  3310. Byte Lane : 08 07 06 05 04 03 02 01 00
  3311. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  3312. Result : P . . . . . . . .
  3313. ResultFound : Y
  3314.  
  3315. Byte Lane : 08 07 06 05 04 03 02 01 00
  3316. DQS Delays : 00 1B 1B 1B 1B 1B 1B 1B 1B
  3317. Result : . . . . . . . .
  3318. ResultFound : Y
  3319.  
  3320. Byte Lane : 08 07 06 05 04 03 02 01 00
  3321. DQS Delays : 00 17 17 17 17 17 17 17 17
  3322. Result : . P . . . P . .
  3323. ResultFound : Y Y Y
  3324.  
  3325. Byte Lane : 08 07 06 05 04 03 02 01 00
  3326. DQS Delays : 00 13 17 13 13 13 17 13 13
  3327. Result : P P P P P P
  3328. ResultFound : Y Y Y Y Y Y Y Y Y
  3329.  
  3330. STAGE: 3 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.
  3331.  
  3332. Byte Lane : 08 07 06 05 04 03 02 01 00
  3333. DQS Delays : 00 14 18 14 14 14 18 14 14
  3334. Result : P P . P P P . P P
  3335. ResultFound : Y Y Y
  3336.  
  3337. Byte Lane : 08 07 06 05 04 03 02 01 00
  3338. DQS Delays : 00 15 18 15 15 15 18 15 15
  3339. Result : P P P P P P
  3340. ResultFound : Y Y Y
  3341.  
  3342. Byte Lane : 08 07 06 05 04 03 02 01 00
  3343. DQS Delays : 00 16 18 16 16 16 18 16 16
  3344. Result : P . P . . P
  3345. ResultFound : Y Y Y Y Y Y
  3346.  
  3347. Byte Lane : 08 07 06 05 04 03 02 01 00
  3348. DQS Delays : 00 17 18 16 17 16 18 16 17
  3349. Result : . . .
  3350. ResultFound : Y Y Y Y Y Y Y Y Y
  3351.  
  3352. Data Eye Results:
  3353.  
  3354. Byte Left Right
  3355. Lane Edge Edge Width Center
  3356. 0 1F 16 17 0B
  3357. 1 1F 15 16 0A
  3358. 2 1F 17 18 0B
  3359. 3 1E 15 17 0A
  3360. 4 1D 16 19 0A
  3361. 5 1E 15 17 0A
  3362. 6 1E 17 19 0B
  3363. 7 1F 16 17 0B
  3364.  
  3365.  
  3366. End HW RxEn Seedless training
  3367.  
  3368.  
  3369. Train WrDat:
  3370.  
  3371. STAGE: 0 Sweeping Write DQS, incrementing from 00 by 04, until all bytelanes PASS.
  3372.  
  3373. Byte Lane : 08 07 06 05 04 03 02 01 00
  3374. DQS Delays : 00 00 00 00 00 00 00 00 00
  3375. Result : P . . . . . . . .
  3376. ResultFound : Y
  3377.  
  3378. Byte Lane : 08 07 06 05 04 03 02 01 00
  3379. DQS Delays : 00 04 04 04 04 04 04 04 04
  3380. Result : P P P P P P P P
  3381. ResultFound : Y Y Y Y Y Y Y Y Y
  3382.  
  3383. STAGE: 1 Sweeping Write DQS, decrementing from Current Delay by 01, until all bytelanes FAIL.
  3384.  
  3385. Byte Lane : 08 07 06 05 04 03 02 01 00
  3386. DQS Delays : 00 03 03 03 03 03 03 03 03
  3387. Result : P P P P P P P P P
  3388. ResultFound : Y
  3389.  
  3390. Byte Lane : 08 07 06 05 04 03 02 01 00
  3391. DQS Delays : 00 02 02 02 02 02 02 02 02
  3392. Result : P P P P P P P .
  3393. ResultFound : Y Y
  3394.  
  3395. Byte Lane : 08 07 06 05 04 03 02 01 00
  3396. DQS Delays : 00 01 01 01 01 01 01 01 02
  3397. Result : . . P P . . .
  3398. ResultFound : Y Y Y Y Y Y Y
  3399.  
  3400. Byte Lane : 08 07 06 05 04 03 02 01 00
  3401. DQS Delays : 00 01 01 00 00 01 01 01 02
  3402. Result : . .
  3403. ResultFound : Y Y Y Y Y Y Y Y Y
  3404.  
  3405. STAGE: 2 Sweeping Write DQS, decrementing from 1F by 04, until all bytelanes PASS.
  3406.  
  3407. Byte Lane : 08 07 06 05 04 03 02 01 00
  3408. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  3409. Result : P . . . . . . . .
  3410. ResultFound : Y
  3411.  
  3412. Byte Lane : 08 07 06 05 04 03 02 01 00
  3413. DQS Delays : 00 1B 1B 1B 1B 1B 1B 1B 1B
  3414. Result : P . . P . . P P
  3415. ResultFound : Y Y Y Y Y
  3416.  
  3417. Byte Lane : 08 07 06 05 04 03 02 01 00
  3418. DQS Delays : 00 1B 17 17 1B 17 17 1B 1B
  3419. Result : P P P P
  3420. ResultFound : Y Y Y Y Y Y Y Y Y
  3421.  
  3422. STAGE: 3 Sweeping Write DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.
  3423.  
  3424. Byte Lane : 08 07 06 05 04 03 02 01 00
  3425. DQS Delays : 00 1C 18 18 1C 18 18 1C 1C
  3426. Result : P . P P . P P . P
  3427. ResultFound : Y Y Y Y
  3428.  
  3429. Byte Lane : 08 07 06 05 04 03 02 01 00
  3430. DQS Delays : 00 1C 19 19 1C 19 19 1C 1D
  3431. Result : P P P P .
  3432. ResultFound : Y Y Y Y Y
  3433.  
  3434. Byte Lane : 08 07 06 05 04 03 02 01 00
  3435. DQS Delays : 00 1C 1A 1A 1C 1A 1A 1C 1D
  3436. Result : P P P P
  3437. ResultFound : Y Y Y Y Y
  3438.  
  3439. Byte Lane : 08 07 06 05 04 03 02 01 00
  3440. DQS Delays : 00 1C 1B 1B 1C 1B 1B 1C 1D
  3441. Result : . . . .
  3442. ResultFound : Y Y Y Y Y Y Y Y Y
  3443.  
  3444. Data Eye Results:
  3445.  
  3446. Byte Left Right
  3447. Lane Edge Edge Width Center
  3448. 0 03 1C 19 10
  3449. 1 02 1B 19 0F
  3450. 2 02 1A 18 0E
  3451. 3 02 1A 18 0E
  3452. 4 01 1B 1A 0E
  3453. 5 01 1A 19 0E
  3454. 6 02 1A 18 0E
  3455. 7 02 1B 19 0F
  3456. CS 3
  3457. Increase WrDat, Train RdDqs:
  3458.  
  3459. Write Delay: 10
  3460.  
  3461. Start HW RxEn Seedless training
  3462.  
  3463. Chip Select: 03
  3464. Byte: 00 01 02 03 04 05 06 07 ECC
  3465. RxEn Orig: 0A8 0AB 0AD 0B7 0B8 0C0 0C8 0D2
  3466. i: 00
  3467.  
  3468. j: 00
  3469. Byte: 00 01 02 03 04 05 06 07 ECC
  3470. Target BL Found: N N N N N N N N
  3471. Target BL Value: 000 000 000 000 000 000 000 000
  3472. Setting PassTestRxEnDly
  3473. PassTestRxEnDly: 0B8 0BB 0BD 0C7 0C8 0D0 0D8 0E2
  3474. OutOfRange: N N N N N N N N
  3475. Checking if PassTestRxEnDly Passes?
  3476.  
  3477. MaxRdLat: 034
  3478. TestAddr: 80200000
  3479. STAGE: 0 Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.
  3480.  
  3481. Byte Lane : 08 07 06 05 04 03 02 01 00
  3482. DQS Delays : 00 00 00 00 00 00 00 00 00
  3483. Result : P P P P P P P P P
  3484. ResultFound : Y
  3485.  
  3486. Byte Lane : 08 07 06 05 04 03 02 01 00
  3487. DQS Delays : 00 1C 1C 1C 1C 1C 1C 1C 1C
  3488. Result : . . . . . . . .
  3489. ResultFound : Y Y Y Y Y Y Y Y Y
  3490.  
  3491. STAGE: 1 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.
  3492.  
  3493. Byte Lane : 08 07 06 05 04 03 02 01 00
  3494. DQS Delays : 00 1D 1D 1D 1D 1D 1D 1D 1D
  3495. Result : P . . . . . . . .
  3496. ResultFound : Y
  3497.  
  3498. Byte Lane : 08 07 06 05 04 03 02 01 00
  3499. DQS Delays : 00 1E 1E 1E 1E 1E 1E 1E 1E
  3500. Result : . . P P P . P P
  3501. ResultFound : Y Y Y Y Y Y
  3502.  
  3503. Byte Lane : 08 07 06 05 04 03 02 01 00
  3504. DQS Delays : 00 1F 1F 1E 1E 1E 1F 1E 1E
  3505. Result : P . .
  3506. ResultFound : Y Y Y Y Y Y Y
  3507.  
  3508. Byte Lane : 08 07 06 05 04 03 02 01 00
  3509. DQS Delays : 00 1F 00 1E 1E 1E 00 1E 1E
  3510. Result : P P
  3511. ResultFound : Y Y Y Y Y Y Y Y Y
  3512.  
  3513. STAGE: 2 Sweeping Read DQS, decrementing from 1F by 04, until all bytelanes PASS.
  3514.  
  3515. Byte Lane : 08 07 06 05 04 03 02 01 00
  3516. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  3517. Result : P . . . . . . . .
  3518. ResultFound : Y
  3519.  
  3520. Byte Lane : 08 07 06 05 04 03 02 01 00
  3521. DQS Delays : 00 1B 1B 1B 1B 1B 1B 1B 1B
  3522. Result : . . . . . . . .
  3523. ResultFound : Y
  3524.  
  3525. Byte Lane : 08 07 06 05 04 03 02 01 00
  3526. DQS Delays : 00 17 17 17 17 17 17 17 17
  3527. Result : . . P . . . P .
  3528. ResultFound : Y Y Y
  3529.  
  3530. Byte Lane : 08 07 06 05 04 03 02 01 00
  3531. DQS Delays : 00 13 13 17 13 13 13 17 13
  3532. Result : P P P P P P
  3533. ResultFound : Y Y Y Y Y Y Y Y Y
  3534.  
  3535. STAGE: 3 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.
  3536.  
  3537. Byte Lane : 08 07 06 05 04 03 02 01 00
  3538. DQS Delays : 00 14 14 18 14 14 14 18 14
  3539. Result : P P P . P P P . P
  3540. ResultFound : Y Y Y
  3541.  
  3542. Byte Lane : 08 07 06 05 04 03 02 01 00
  3543. DQS Delays : 00 15 15 18 15 15 15 18 15
  3544. Result : P P P P P P
  3545. ResultFound : Y Y Y
  3546.  
  3547. Byte Lane : 08 07 06 05 04 03 02 01 00
  3548. DQS Delays : 00 16 16 18 16 16 16 18 16
  3549. Result : . . . P . .
  3550. ResultFound : Y Y Y Y Y Y Y Y
  3551.  
  3552. Byte Lane : 08 07 06 05 04 03 02 01 00
  3553. DQS Delays : 00 16 16 18 16 17 16 18 16
  3554. Result : .
  3555. ResultFound : Y Y Y Y Y Y Y Y Y
  3556.  
  3557. Data Eye Results:
  3558.  
  3559. Byte Left Right
  3560. Lane Edge Edge Width Center
  3561. 0 1E 15 17 0A
  3562. 1 1E 17 19 0B
  3563. 2 00 15 15 0B
  3564. 3 1E 16 18 0A
  3565. 4 1E 15 17 0A
  3566. 5 1E 17 19 0B
  3567. 6 00 15 15 0B
  3568. 7 1F 15 16 0A
  3569.  
  3570. Byte: 00 01 02 03 04 05 06 07 ECC
  3571. Err Status: P P P P P P P P
  3572. Byte: 00 01 02 03 04 05 06 07 ECC
  3573. FailTestRxEnDly: 0F8 0FB 0FD 107 108 110 118 122
  3574. Setting FailTestRxEnDly
  3575. OutOfRange: N N N N N N N N
  3576. FailTestRxEnDly: Y Y Y Y Y Y Y Y
  3577.  
  3578. Checking if FailTestRxEnDly Fails?
  3579. MaxRdLat: 037
  3580. TestAddr: 80200000
  3581. STAGE: 0 Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.
  3582.  
  3583. Byte Lane : 08 07 06 05 04 03 02 01 00
  3584. DQS Delays : 00 00 00 00 00 00 00 00 00
  3585. Result : P . . . . . . . .
  3586. ResultFound : Y Y Y Y Y Y Y Y Y
  3587.  
  3588. STAGE: 1 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.
  3589.  
  3590. Byte Lane : 08 07 06 05 04 03 02 01 00
  3591. DQS Delays : 00 01 01 01 01 01 01 01 01
  3592. Result : P . . . . . . . .
  3593. ResultFound : Y
  3594.  
  3595. Byte Lane : 08 07 06 05 04 03 02 01 00
  3596. DQS Delays : 00 02 02 02 02 02 02 02 02
  3597. Result : . . . . . . . .
  3598. ResultFound : Y
  3599.  
  3600. Byte Lane : 08 07 06 05 04 03 02 01 00
  3601. DQS Delays : 00 03 03 03 03 03 03 03 03
  3602. Result : . . . . . . . .
  3603. ResultFound : Y
  3604.  
  3605. Byte Lane : 08 07 06 05 04 03 02 01 00
  3606. DQS Delays : 00 04 04 04 04 04 04 04 04
  3607. Result : . . . . . . . .
  3608. ResultFound : Y
  3609.  
  3610. Byte Lane : 08 07 06 05 04 03 02 01 00
  3611. DQS Delays : 00 05 05 05 05 05 05 05 05
  3612. Result : . . . . . . . .
  3613. ResultFound : Y
  3614.  
  3615. Byte Lane : 08 07 06 05 04 03 02 01 00
  3616. DQS Delays : 00 06 06 06 06 06 06 06 06
  3617. Result : . . . . . . . .
  3618. ResultFound : Y
  3619.  
  3620. Byte Lane : 08 07 06 05 04 03 02 01 00
  3621. DQS Delays : 00 07 07 07 07 07 07 07 07
  3622. Result : . . . . . . . .
  3623. ResultFound : Y
  3624.  
  3625. Byte Lane : 08 07 06 05 04 03 02 01 00
  3626. DQS Delays : 00 08 08 08 08 08 08 08 08
  3627. Result : . . . . . . . .
  3628. ResultFound : Y
  3629.  
  3630. Byte Lane : 08 07 06 05 04 03 02 01 00
  3631. DQS Delays : 00 09 09 09 09 09 09 09 09
  3632. Result : . . . . . . . .
  3633. ResultFound : Y
  3634.  
  3635. Byte Lane : 08 07 06 05 04 03 02 01 00
  3636. DQS Delays : 00 0A 0A 0A 0A 0A 0A 0A 0A
  3637. Result : . . . . . . . .
  3638. ResultFound : Y
  3639.  
  3640. Byte Lane : 08 07 06 05 04 03 02 01 00
  3641. DQS Delays : 00 0B 0B 0B 0B 0B 0B 0B 0B
  3642. Result : . . . . . . . .
  3643. ResultFound : Y
  3644.  
  3645. Byte Lane : 08 07 06 05 04 03 02 01 00
  3646. DQS Delays : 00 0C 0C 0C 0C 0C 0C 0C 0C
  3647. Result : . . . . . . . .
  3648. ResultFound : Y
  3649.  
  3650. Byte Lane : 08 07 06 05 04 03 02 01 00
  3651. DQS Delays : 00 0D 0D 0D 0D 0D 0D 0D 0D
  3652. Result : . . . . . . . .
  3653. ResultFound : Y
  3654.  
  3655. Byte Lane : 08 07 06 05 04 03 02 01 00
  3656. DQS Delays : 00 0E 0E 0E 0E 0E 0E 0E 0E
  3657. Result : . . . . . . . .
  3658. ResultFound : Y
  3659.  
  3660. Byte Lane : 08 07 06 05 04 03 02 01 00
  3661. DQS Delays : 00 0F 0F 0F 0F 0F 0F 0F 0F
  3662. Result : . . . . . . . .
  3663. ResultFound : Y
  3664.  
  3665. Byte Lane : 08 07 06 05 04 03 02 01 00
  3666. DQS Delays : 00 10 10 10 10 10 10 10 10
  3667. Result : . . . . . . . .
  3668. ResultFound : Y
  3669.  
  3670. Byte Lane : 08 07 06 05 04 03 02 01 00
  3671. DQS Delays : 00 11 11 11 11 11 11 11 11
  3672. Result : . . . . . . . .
  3673. ResultFound : Y
  3674.  
  3675. Byte Lane : 08 07 06 05 04 03 02 01 00
  3676. DQS Delays : 00 12 12 12 12 12 12 12 12
  3677. Result : . . . . . . . .
  3678. ResultFound : Y
  3679.  
  3680. Byte Lane : 08 07 06 05 04 03 02 01 00
  3681. DQS Delays : 00 13 13 13 13 13 13 13 13
  3682. Result : . . . . . . . .
  3683. ResultFound : Y
  3684.  
  3685. Byte Lane : 08 07 06 05 04 03 02 01 00
  3686. DQS Delays : 00 14 14 14 14 14 14 14 14
  3687. Result : . . . . . . . .
  3688. ResultFound : Y
  3689.  
  3690. Byte Lane : 08 07 06 05 04 03 02 01 00
  3691. DQS Delays : 00 15 15 15 15 15 15 15 15
  3692. Result : . . . . . . . .
  3693. ResultFound : Y
  3694.  
  3695. Byte Lane : 08 07 06 05 04 03 02 01 00
  3696. DQS Delays : 00 16 16 16 16 16 16 16 16
  3697. Result : . . . . . . . .
  3698. ResultFound : Y
  3699.  
  3700. Byte Lane : 08 07 06 05 04 03 02 01 00
  3701. DQS Delays : 00 17 17 17 17 17 17 17 17
  3702. Result : . . . . . . . .
  3703. ResultFound : Y
  3704.  
  3705. Byte Lane : 08 07 06 05 04 03 02 01 00
  3706. DQS Delays : 00 18 18 18 18 18 18 18 18
  3707. Result : . . . . . . . .
  3708. ResultFound : Y
  3709.  
  3710. Byte Lane : 08 07 06 05 04 03 02 01 00
  3711. DQS Delays : 00 19 19 19 19 19 19 19 19
  3712. Result : . . . . . . . .
  3713. ResultFound : Y
  3714.  
  3715. Byte Lane : 08 07 06 05 04 03 02 01 00
  3716. DQS Delays : 00 1A 1A 1A 1A 1A 1A 1A 1A
  3717. Result : . . . . . . . .
  3718. ResultFound : Y
  3719.  
  3720. Byte Lane : 08 07 06 05 04 03 02 01 00
  3721. DQS Delays : 00 1B 1B 1B 1B 1B 1B 1B 1B
  3722. Result : . . . . . . . .
  3723. ResultFound : Y
  3724.  
  3725. Byte Lane : 08 07 06 05 04 03 02 01 00
  3726. DQS Delays : 00 1C 1C 1C 1C 1C 1C 1C 1C
  3727. Result : . . . . . . . .
  3728. ResultFound : Y
  3729.  
  3730. Byte Lane : 08 07 06 05 04 03 02 01 00
  3731. DQS Delays : 00 1D 1D 1D 1D 1D 1D 1D 1D
  3732. Result : . . . . . . . .
  3733. ResultFound : Y
  3734.  
  3735. Byte Lane : 08 07 06 05 04 03 02 01 00
  3736. DQS Delays : 00 1E 1E 1E 1E 1E 1E 1E 1E
  3737. Result : . . . . . . . .
  3738. ResultFound : Y
  3739.  
  3740. Byte Lane : 08 07 06 05 04 03 02 01 00
  3741. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  3742. Result : . . . . . . . .
  3743. ResultFound : Y
  3744.  
  3745. --DATA EYE NOT FOUND--
  3746.  
  3747.  
  3748. Byte: 00 01 02 03 04 05 06 07 ECC
  3749. Err Status: F F F F F F F F
  3750. Set FinalRxEnCycle: Y Y Y Y Y Y Y Y
  3751. OutOfRange: N N N N N N N N
  3752. FinalRxEnCycle: 0A8 0AB 0AD 0B7 0B8 0C0 0C8 0D2
  3753. ByteLaneFail: Y Y Y Y Y Y Y Y
  3754. ByteLanePass: Y Y Y Y Y Y Y Y
  3755.  
  3756. Setting new RDQS based on FinalRxEnCycle
  3757.  
  3758. MaxRdLat: 033
  3759. TestAddr: 80200000
  3760. STAGE: 0 Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.
  3761.  
  3762. Byte Lane : 08 07 06 05 04 03 02 01 00
  3763. DQS Delays : 00 00 00 00 00 00 00 00 00
  3764. Result : P P P P P P P P P
  3765. ResultFound : Y
  3766.  
  3767. Byte Lane : 08 07 06 05 04 03 02 01 00
  3768. DQS Delays : 00 1C 1C 1C 1C 1C 1C 1C 1C
  3769. Result : . . . . . . . .
  3770. ResultFound : Y Y Y Y Y Y Y Y Y
  3771.  
  3772. STAGE: 1 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.
  3773.  
  3774. Byte Lane : 08 07 06 05 04 03 02 01 00
  3775. DQS Delays : 00 1D 1D 1D 1D 1D 1D 1D 1D
  3776. Result : P . . . . P . . .
  3777. ResultFound : Y Y
  3778.  
  3779. Byte Lane : 08 07 06 05 04 03 02 01 00
  3780. DQS Delays : 00 1E 1E 1E 1E 1D 1E 1E 1E
  3781. Result : . . P P . P .
  3782. ResultFound : Y Y Y Y Y
  3783.  
  3784. Byte Lane : 08 07 06 05 04 03 02 01 00
  3785. DQS Delays : 00 1F 1F 1E 1E 1D 1F 1E 1F
  3786. Result : P . . P
  3787. ResultFound : Y Y Y Y Y Y Y
  3788.  
  3789. Byte Lane : 08 07 06 05 04 03 02 01 00
  3790. DQS Delays : 00 1F 00 1E 1E 1D 00 1E 1F
  3791. Result : P P
  3792. ResultFound : Y Y Y Y Y Y Y Y Y
  3793.  
  3794. STAGE: 2 Sweeping Read DQS, decrementing from 1F by 04, until all bytelanes PASS.
  3795.  
  3796. Byte Lane : 08 07 06 05 04 03 02 01 00
  3797. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  3798. Result : P . . . . . . . .
  3799. ResultFound : Y
  3800.  
  3801. Byte Lane : 08 07 06 05 04 03 02 01 00
  3802. DQS Delays : 00 1B 1B 1B 1B 1B 1B 1B 1B
  3803. Result : . . . . . . . .
  3804. ResultFound : Y
  3805.  
  3806. Byte Lane : 08 07 06 05 04 03 02 01 00
  3807. DQS Delays : 00 17 17 17 17 17 17 17 17
  3808. Result : . . . . . . . .
  3809. ResultFound : Y
  3810.  
  3811. Byte Lane : 08 07 06 05 04 03 02 01 00
  3812. DQS Delays : 00 13 13 13 13 13 13 13 13
  3813. Result : P P P P P P P P
  3814. ResultFound : Y Y Y Y Y Y Y Y Y
  3815.  
  3816. STAGE: 3 Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.
  3817.  
  3818. Byte Lane : 08 07 06 05 04 03 02 01 00
  3819. DQS Delays : 00 14 14 14 14 14 14 14 14
  3820. Result : P P P P P P P P P
  3821. ResultFound : Y
  3822.  
  3823. Byte Lane : 08 07 06 05 04 03 02 01 00
  3824. DQS Delays : 00 15 15 15 15 15 15 15 15
  3825. Result : P P P P P P P P
  3826. ResultFound : Y
  3827.  
  3828. Byte Lane : 08 07 06 05 04 03 02 01 00
  3829. DQS Delays : 00 16 16 16 16 16 16 16 16
  3830. Result : P . P . P . P .
  3831. ResultFound : Y Y Y Y Y
  3832.  
  3833. Byte Lane : 08 07 06 05 04 03 02 01 00
  3834. DQS Delays : 00 17 16 17 16 17 16 17 16
  3835. Result : . P . P
  3836. ResultFound : Y Y Y Y Y Y Y
  3837.  
  3838. Byte Lane : 08 07 06 05 04 03 02 01 00
  3839. DQS Delays : 00 17 16 18 16 17 16 18 16
  3840. Result : . .
  3841. ResultFound : Y Y Y Y Y Y Y Y Y
  3842.  
  3843. Data Eye Results:
  3844.  
  3845. Byte Left Right
  3846. Lane Edge Edge Width Center
  3847. 0 1F 15 16 0A
  3848. 1 1E 17 19 0B
  3849. 2 00 15 15 0B
  3850. 3 1D 16 19 0A
  3851. 4 1E 15 17 0A
  3852. 5 1E 17 19 0B
  3853. 6 00 15 15 0B
  3854. 7 1F 16 17 0B
  3855.  
  3856.  
  3857. End HW RxEn Seedless training
  3858.  
  3859.  
  3860. Train WrDat:
  3861.  
  3862. STAGE: 0 Sweeping Write DQS, incrementing from 00 by 04, until all bytelanes PASS.
  3863.  
  3864. Byte Lane : 08 07 06 05 04 03 02 01 00
  3865. DQS Delays : 00 00 00 00 00 00 00 00 00
  3866. Result : P . . . . . . . .
  3867. ResultFound : Y
  3868.  
  3869. Byte Lane : 08 07 06 05 04 03 02 01 00
  3870. DQS Delays : 00 04 04 04 04 04 04 04 04
  3871. Result : P P P P P P P P
  3872. ResultFound : Y Y Y Y Y Y Y Y Y
  3873.  
  3874. STAGE: 1 Sweeping Write DQS, decrementing from Current Delay by 01, until all bytelanes FAIL.
  3875.  
  3876. Byte Lane : 08 07 06 05 04 03 02 01 00
  3877. DQS Delays : 00 03 03 03 03 03 03 03 03
  3878. Result : P P P P P P P P P
  3879. ResultFound : Y
  3880.  
  3881. Byte Lane : 08 07 06 05 04 03 02 01 00
  3882. DQS Delays : 00 02 02 02 02 02 02 02 02
  3883. Result : . P . P . P P P
  3884. ResultFound : Y Y Y Y
  3885.  
  3886. Byte Lane : 08 07 06 05 04 03 02 01 00
  3887. DQS Delays : 00 02 01 02 01 02 01 01 01
  3888. Result : . . P . .
  3889. ResultFound : Y Y Y Y Y Y Y Y
  3890.  
  3891. Byte Lane : 08 07 06 05 04 03 02 01 00
  3892. DQS Delays : 00 02 01 02 01 02 00 01 01
  3893. Result : .
  3894. ResultFound : Y Y Y Y Y Y Y Y Y
  3895.  
  3896. STAGE: 2 Sweeping Write DQS, decrementing from 1F by 04, until all bytelanes PASS.
  3897.  
  3898. Byte Lane : 08 07 06 05 04 03 02 01 00
  3899. DQS Delays : 00 1F 1F 1F 1F 1F 1F 1F 1F
  3900. Result : P . . . . . . . .
  3901. ResultFound : Y
  3902.  
  3903. Byte Lane : 08 07 06 05 04 03 02 01 00
  3904. DQS Delays : 00 1B 1B 1B 1B 1B 1B 1B 1B
  3905. Result : . . . . . . . P
  3906. ResultFound : Y Y
  3907.  
  3908. Byte Lane : 08 07 06 05 04 03 02 01 00
  3909. DQS Delays : 00 17 17 17 17 17 17 17 1B
  3910. Result : P P P P P P P
  3911. ResultFound : Y Y Y Y Y Y Y Y Y
  3912.  
  3913. STAGE: 3 Sweeping Write DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.
  3914.  
  3915. Byte Lane : 08 07 06 05 04 03 02 01 00
  3916. DQS Delays : 00 18 18 18 18 18 18 18 1C
  3917. Result : P P P P P P P P .
  3918. ResultFound : Y Y
  3919.  
  3920. Byte Lane : 08 07 06 05 04 03 02 01 00
  3921. DQS Delays : 00 19 19 19 19 19 19 19 1C
  3922. Result : P P P P P P P
  3923. ResultFound : Y Y
  3924.  
  3925. Byte Lane : 08 07 06 05 04 03 02 01 00
  3926. DQS Delays : 00 1A 1A 1A 1A 1A 1A 1A 1C
  3927. Result : P . . P . . .
  3928. ResultFound : Y Y Y Y Y Y Y
  3929.  
  3930. Byte Lane : 08 07 06 05 04 03 02 01 00
  3931. DQS Delays : 00 1B 1A 1A 1B 1A 1A 1A 1C
  3932. Result : . P
  3933. ResultFound : Y Y Y Y Y Y Y Y
  3934.  
  3935. Byte Lane : 08 07 06 05 04 03 02 01 00
  3936. DQS Delays : 00 1B 1A 1A 1C 1A 1A 1A 1C
  3937. Result : .
  3938. ResultFound : Y Y Y Y Y Y Y Y Y
  3939.  
  3940. Data Eye Results:
  3941.  
  3942. Byte Left Right
  3943. Lane Edge Edge Width Center
  3944. 0 02 1B 19 0F
  3945. 1 02 19 17 0E
  3946. 2 01 19 18 0D
  3947. 3 03 19 16 0E
  3948. 4 02 1B 19 0F
  3949. 5 03 19 16 0E
  3950. 6 02 19 17 0E
  3951. 7 03 1A 17 0F
  3952. End Read/Write Data Eye Edge Detection
  3953.  
  3954. MemFInitTableDrive [000000000000000E] Start
  3955. MemFInitTableDrive End
  3956.  
  3957. Going into training stage 3. Partial training at all frequencies is done.
  3958.  
  3959. Start MaxRdLat training
  3960. Dct 0
  3961. Dct 1
  3962. CS 3
  3963. Write to address: 80200000
  3964. Dly 26
  3965. Dly 27
  3966. Dly 28
  3967. Dly 29
  3968. Dly 2A
  3969. Dly 2B
  3970. Dly 2C
  3971. Dly 2D
  3972. Dly 2E
  3973. Dly 2F P Final MaxRdLat: 035
  3974. End MaxRdLat training
  3975.  
  3976. MemFInitTableDrive [000000000000000F] Start
  3977. MemFInitTableDrive End
  3978. F15TnGetNbPstateInfo - NB P0
  3979. En:1 Fid:E Did:0 Vid:44
  3980. F15TnGetNbFreqNumeratorInMHz - NbFid=14
  3981. FreqNumeratorInMHz=1800
  3982. F15TnGetNbFreqDivisor - NbDid=0
  3983. FreqDivisor=1
  3984. F15TnCovertVidInuV
  3985. Vid=44, VoltageInuV=1125000
  3986. NB Pstate 0 is Valid. NbVid=68 VoltageInuV=1125000
  3987. Memclk Freq: 667
  3988. RdPtr: 6
  3989. MemFInitTableDrive [0000000000000010] Start
  3990. MemFInitTableDrive End
  3991. F15TnGetNbPstateInfo - NB P1
  3992. F15TnGetNbPstateInfo - NB P2
  3993. F15TnGetNbPstateInfo - NB P3
  3994. F15TnGetPstateFrequency - P3
  3995. FrequencyInMHz=3900, CpuFid=23, CpuDid=0
  3996. Release NB Pstate force
  3997.  
  3998. End DQS training
  3999.  
  4000.  
  4001. Start Programming of Non-SPD Timings.
  4002. Dct 0
  4003. Dct 1
  4004. LD: 2 ROD: 0 WOD: 0 WrEarlyx2: 0
  4005.  
  4006. TrdrdSdSc : 01
  4007. CDDTrdrdSdDc : 01 TrdrdSdDc : 04
  4008. CDDTrdrdDd : FFFFFF81 TrdrdDd : 04
  4009.  
  4010. TwrwrSdSc : 01
  4011. CDDTwrwrSdDc : 00 TwrwrSdDc : 04
  4012. CDDTwrwrDd : FFFFFF81 TwrwrDd : 04
  4013.  
  4014. TrwtWB : 08
  4015. CDDTwrrd : FC Twrrd : 01
  4016. CDDTrwtTO : 05 TrwtTO : 07
  4017.  
  4018. MemFInitTableDrive [0000000000000006] Start
  4019. MemFInitTableDrive End
  4020.  
  4021. * WARNING Event: 04012100 Data: 0, 0, 0, 0
  4022.  
  4023.  
  4024. * WARNING Event: 04012200 Data: 0, 0, 0, 0
  4025.  
  4026. MemFInitTableDrive [0000000000000011] Start
  4027. MemFInitTableDrive End
  4028. TOP_MEM2: 00011F000000
  4029. UMA is allocated:
  4030. Base: C0000000
  4031. Size: 20000000
  4032. Dct 0
  4033. ODTSEn = 0
  4034. ExtendTmp = 0
  4035. Dct 1
  4036. ODTSEn = 0
  4037. ExtendTmp = 0
  4038. Start Phy power saving setting for memory Pstate 0
  4039. Start Phy power saving setting for memory Pstate 1
  4040. MemFInitTableDrive [0000000000000012] Start
  4041. MemFInitTableDrive End
  4042. MemFInitTableDrive [0000000000000013] Start
  4043. MemFInitTableDrive End
  4044.  
  4045. Save memory S3 data in heap
  4046.  
  4047. * BOUNDS_CHK Event: 08040100 Data: 1240000, 0, 0, 0
  4048.  
  4049.  
  4050. * BOUNDS_CHK Event: 08040100 Data: 1241000, 0, 0, 0
  4051.  
  4052.  
  4053. * BOUNDS_CHK Event: 08040100 Data: 1242000, 0, 0, 0
  4054.  
  4055.  
  4056. * BOUNDS_CHK Event: 08040100 Data: 1243000, 0, 0, 0
  4057.  
  4058.  
  4059. * BOUNDS_CHK Event: 08040100 Data: 1244000, 0, 0, 0
  4060.  
  4061.  
  4062. * BOUNDS_CHK Event: 08040100 Data: 1245000, 0, 0, 0
  4063.  
  4064.  
  4065. * BOUNDS_CHK Event: 08040100 Data: 1246000, 0, 0, 0
  4066.  
  4067. AmdMemAuto: End
  4068. AmdCpuPost: Start
  4069. Dispatch CPU features after AP MTRR sync
  4070. C6 is enabled
  4071. Cache flush on hlt feature is enabled
  4072. HTC is being initialized
  4073. HTC is enabled
  4074. Perform feature leveling
  4075. Create P-state info in the heap
  4076. F15TnGetPstateMaxState
  4077. MaxPStateNumber=7, NumBoostStates=3
  4078. F15TnGetPstateMaxState
  4079. MaxPStateNumber=7, NumBoostStates=3
  4080. F15TnGetPstateRegisterInfo - P0
  4081. Pstate 0 is enabled. SwPstateNumber=0
  4082. IddVal=183, IddDiv=1
  4083. F15TnGetPstateRegisterInfo - P1
  4084. Pstate 1 is enabled. SwPstateNumber=1
  4085. IddVal=209, IddDiv=1
  4086. F15TnGetPstateRegisterInfo - P2
  4087. Pstate 2 is enabled. SwPstateNumber=2
  4088. IddVal=192, IddDiv=1
  4089. F15TnGetPstateRegisterInfo - P3
  4090. Pstate 3 is enabled. SwPstateNumber=0
  4091. IddVal=155, IddDiv=1
  4092. F15TnGetPstateFrequency - P3
  4093. FrequencyInMHz=3900, CpuFid=23, CpuDid=0
  4094. F15TnGetPstatePower - P3
  4095. PowerInMw=20731, CpuVid=34, IddValue=155, IddDiv=1
  4096. F15TnGetPstateRegisterInfo - P4
  4097. Pstate 4 is enabled. SwPstateNumber=1
  4098. IddVal=128, IddDiv=1
  4099. F15TnGetPstateFrequency - P4
  4100. FrequencyInMHz=3600, CpuFid=20, CpuDid=0
  4101. F15TnGetPstatePower - P4
  4102. PowerInMw=16000, CpuVid=48, IddValue=128, IddDiv=1
  4103. F15TnGetPstateRegisterInfo - P5
  4104. Pstate 5 is enabled. SwPstateNumber=2
  4105. IddVal=91, IddDiv=1
  4106. F15TnGetPstateFrequency - P5
  4107. FrequencyInMHz=3000, CpuFid=14, CpuDid=0
  4108. F15TnGetPstatePower - P5
  4109. PowerInMw=10237, CpuVid=68, IddValue=91, IddDiv=1
  4110. F15TnGetPstateRegisterInfo - P6
  4111. Pstate 6 is enabled. SwPstateNumber=3
  4112. IddVal=64, IddDiv=1
  4113. F15TnGetPstateFrequency - P6
  4114. FrequencyInMHz=2500, CpuFid=9, CpuDid=0
  4115. F15TnGetPstatePower - P6
  4116. PowerInMw=6480, CpuVid=86, IddValue=64, IddDiv=1
  4117. F15TnGetPstateRegisterInfo - P7
  4118. Pstate 7 is enabled. SwPstateNumber=4
  4119. IddVal=43, IddDiv=1
  4120. F15TnGetPstateFrequency - P7
  4121. FrequencyInMHz=1900, CpuFid=3, CpuDid=0
  4122. F15TnGetPstatePower - P7
  4123. PowerInMw=3923, CpuVid=102, IddValue=43, IddDiv=1
  4124. F15TnSetTscFreqSel
  4125. F15TnSetTscFreqSel
  4126. F15TnSetTscFreqSel
  4127. F15TnSetTscFreqSel
  4128. Dispatch CPU features before Relinquishing control of APs
  4129. Relinquish control of APs
  4130. AmdCpuPost: End
  4131. GnbPostInterfaceTN Enter
  4132.  
  4133. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4134.  
  4135.  
  4136. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4137.  
  4138.  
  4139. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4140.  
  4141.  
  4142. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4143.  
  4144.  
  4145. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4146.  
  4147. GnbPostInterfaceTN Exit [0x0]
  4148. PciePostInterfaceTN Enter
  4149.  
  4150. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4151.  
  4152.  
  4153. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4154.  
  4155.  
  4156. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4157.  
  4158.  
  4159. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4160.  
  4161. PcieSetVoltageTN Enter
  4162.  
  4163. * BOUNDS_CHK Event: 08040100 Data: A021, 0, 0, 0
  4164.  
  4165. Set Voltage for Gen 2, Vid code 80
  4166. R WRITE Space TYPE_GMM Address 0x063C, Value 0x6006
  4167.  
  4168. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4169.  
  4170.  
  4171. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4172.  
  4173. R WRITE Space TYPE_GMM Address 0x063C, Value 0x5002
  4174.  
  4175. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4176.  
  4177.  
  4178. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4179.  
  4180. PcieSetVoltageTN Exit
  4181. PcieTraining Enter
  4182. PcieTraining Exit [0]
  4183. PcieSiliconHidePorts Enter
  4184.  
  4185. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4186.  
  4187.  
  4188. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4189.  
  4190.  
  4191. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4192.  
  4193.  
  4194. * BOUNDS_CHK Event: 08040100 Data: A00A, 0, 0, 0
  4195.  
  4196. Write D0F0x64_x0C.Value = FC
  4197. PcieSiliconHidePorts Exit
  4198. PciePostInterfaceTN Exit [0x0]
  4199.  
  4200. AmdInitPost: End
  4201.  
  4202. Heap transfer Start ...
  4203.  
  4204.  
  4205. EventLog: EventClass = 2, EventInfo = 8040100.
  4206. Param1 = a00a, Param2 = 0.
  4207. Param3 = 0, Param4 = 0.
  4208.  
  4209. EventLog: EventClass = 2, EventInfo = 8040100.
  4210. Param1 = a00a, Param2 = 0.
  4211. Param3 = 0, Param4 = 0.
  4212.  
  4213. EventLog: EventClass = 2, EventInfo = 8040100.
  4214. Param1 = a00a, Param2 = 0.
  4215. Param3 = 0, Param4 = 0.
  4216.  
  4217. EventLog: EventClass = 2, EventInfo = 8040100.
  4218. Param1 = a00a, Param2 = 0.
  4219. Param3 = 0, Param4 = 0.
  4220.  
  4221. EventLog: EventClass = 2, EventInfo = 8040100.
  4222. Param1 = a00a, Param2 = 0.
  4223. Param3 = 0, Param4 = 0.
  4224.  
  4225. EventLog: EventClass = 2, EventInfo = 8040100.
  4226. Param1 = a00a, Param2 = 0.
  4227. Param3 = 0, Param4 = 0.
  4228.  
  4229. EventLog: EventClass = 2, EventInfo = 8040100.
  4230. Param1 = a00a, Param2 = 0.
  4231. Param3 = 0, Param4 = 0.
  4232.  
  4233. EventLog: EventClass = 2, EventInfo = 8040100.
  4234. Param1 = a021, Param2 = 0.
  4235. Param3 = 0, Param4 = 0.
  4236.  
  4237. EventLog: EventClass = 2, EventInfo = 8040100.
  4238. Param1 = a00a, Param2 = 0.
  4239. Param3 = 0, Param4 = 0.
  4240.  
  4241. EventLog: EventClass = 2, EventInfo = 8040100.
  4242. Param1 = a00a, Param2 = 0.
  4243. Param3 = 0, Param4 = 0.
  4244.  
  4245. EventLog: EventClass = 2, EventInfo = 8040100.
  4246. Param1 = a00a, Param2 = 0.
  4247. Param3 = 0, Param4 = 0.
  4248.  
  4249. EventLog: EventClass = 2, EventInfo = 8040100.
  4250. Param1 = a00a, Param2 = 0.
  4251. Param3 = 0, Param4 = 0.
  4252.  
  4253. EventLog: EventClass = 2, EventInfo = 8040100.
  4254. Param1 = a00a, Param2 = 0.
  4255. Param3 = 0, Param4 = 0.
  4256.  
  4257. EventLog: EventClass = 2, EventInfo = 8040100.
  4258. Param1 = a00a, Param2 = 0.
  4259. Param3 = 0, Param4 = 0.
  4260.  
  4261. EventLog: EventClass = 2, EventInfo = 8040100.
  4262. Param1 = a00a, Param2 = 0.
  4263. Param3 = 0, Param4 = 0.
  4264.  
  4265. EventLog: EventClass = 2, EventInfo = 8040100.
  4266. Param1 = a00a, Param2 = 0.
  4267. Param3 = 0, Param4 = 0.
  4268.  
  4269. * BOUNDS_CHK Event: 08040100 Data: 1180000, 0, 0, 0
  4270.  
  4271.  
  4272. * BOUNDS_CHK Event: 08040100 Data: 1080000, 0, 0, 0
  4273.  
  4274.  
  4275. * BOUNDS_CHK Event: 08040100 Data: 1040000, 0, 0, 0
  4276.  
  4277.  
  4278. * BOUNDS_CHK Event: 08040100 Data: A008, 0, 0, 0
  4279.  
  4280.  
  4281. * BOUNDS_CHK Event: 08040100 Data: A00F, 0, 0, 0
  4282.  
  4283.  
  4284. * BOUNDS_CHK Event: 08040100 Data: A00E, 0, 0, 0
  4285.  
  4286.  
  4287. * BOUNDS_CHK Event: 08040100 Data: A010, 0, 0, 0
  4288.  
  4289. agesawrapper_amdinitpost failed: 4
  4290. Got past agesawrapper_amdinitpost
  4291. Heap transfer End
  4292. AmdInitEnv: Start
  4293.  
  4294. FchInitEnv Enter...
  4295. FCH Data Block Allocation: [0x0], Ptr = 0x1001202C
  4296. Fch OEM config in INIT ENV Done
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!