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  1. From 5c95baa23c6a85b8052518c63e9d1c00ca60e718 Mon Sep 17 00:00:00 2001
  2. From: Andy Pugh <andy@bodgesoc.org>
  3. Date: Fri, 26 Aug 2011 21:26:18 +0100
  4. Subject: [PATCH] Add support for Mesa 5i21, 5i25 and 4i69 FPGA cards.
  5.  
  6. Signed-off-by: Peter C. Wallace <pcw@mesanet.com>
  7. ---
  8. src/hal/drivers/mesa-hostmot2/hm2_pci.c | 130 +++++++++++++++++++++++++-----
  9. src/hal/drivers/mesa-hostmot2/hm2_pci.h | 14 +++-
  10. src/hal/drivers/mesa-hostmot2/hostmot2.c | 11 +---
  11. src/hal/drivers/mesa-hostmot2/pins.c | 32 +++++++-
  12. 4 files changed, 151 insertions(+), 36 deletions(-)
  13.  
  14. diff --git a/src/hal/drivers/mesa-hostmot2/hm2_pci.c b/src/hal/drivers/mesa-hostmot2/hm2_pci.c
  15. index 1a4f046..9ea6de1 100644
  16. --- a/src/hal/drivers/mesa-hostmot2/hm2_pci.c
  17. +++ b/src/hal/drivers/mesa-hostmot2/hm2_pci.c
  18. @@ -33,7 +33,7 @@
  19.  
  20. MODULE_LICENSE("GPL");
  21. MODULE_AUTHOR("Sebastian Kuzminsky");
  22. -MODULE_DESCRIPTION("Driver for HostMot2 on the 5i2[023], 4i6[58], and 3x20 Anything I/O boards from Mesa Electronics");
  23. +MODULE_DESCRIPTION("Driver for HostMot2 on the 5i2[01235], 4i6[589], and 3x20 Anything I/O boards from Mesa Electronics");
  24. MODULE_SUPPORTED_DEVICE("Mesa-AnythingIO-5i20"); // FIXME
  25.  
  26.  
  27. @@ -50,10 +50,13 @@ static int comp_id;
  28. static hm2_pci_t hm2_pci_board[HM2_PCI_MAX_BOARDS];
  29. static int num_boards = 0;
  30. static int num_5i20 = 0;
  31. +static int num_5i21 = 0;
  32. static int num_5i22 = 0;
  33. static int num_5i23 = 0;
  34. +static int num_5i25 = 0;
  35. static int num_4i65 = 0;
  36. static int num_4i68 = 0;
  37. +static int num_4i69 = 0;
  38. static int num_3x20 = 0;
  39. static int failed_errno=0; // errno of last failed registration
  40.  
  41. @@ -62,81 +65,113 @@ static struct pci_device_id hm2_pci_tbl[] = {
  42.  
  43. // 5i20
  44. {
  45. - .vendor = 0x10b5,
  46. + .vendor = HM2_PCI_VENDORID_PLX,
  47. .device = HM2_PCI_DEV_PLX9030,
  48. - .subvendor = 0x10b5,
  49. + .subvendor = HM2_PCI_VENDORID_PLX,
  50. .subdevice = HM2_PCI_SSDEV_5I20,
  51. },
  52.  
  53. + // 5i21
  54. + {
  55. + .vendor = HM2_PCI_VENDORID_PLX,
  56. + .device = HM2_PCI_DEV_PLX9054,
  57. + .subvendor = HM2_PCI_VENDORID_PLX,
  58. + .subdevice = HM2_PCI_SSDEV_5I21,
  59. + },
  60. +
  61. // 4i65
  62. {
  63. - .vendor = 0x10b5,
  64. + .vendor = HM2_PCI_VENDORID_PLX,
  65. .device = HM2_PCI_DEV_PLX9030,
  66. - .subvendor = 0x10b5,
  67. + .subvendor = HM2_PCI_VENDORID_PLX,
  68. .subdevice = HM2_PCI_SSDEV_4I65,
  69. },
  70.  
  71. // 5i22-1.0M
  72. {
  73. - .vendor = 0x10b5,
  74. + .vendor = HM2_PCI_VENDORID_PLX,
  75. .device = HM2_PCI_DEV_PLX9054,
  76. - .subvendor = 0x10b5,
  77. + .subvendor = HM2_PCI_VENDORID_PLX,
  78. .subdevice = HM2_PCI_SSDEV_5I22_10,
  79. },
  80.  
  81. // 5i22-1.5M
  82. {
  83. - .vendor = 0x10b5,
  84. + .vendor = HM2_PCI_VENDORID_PLX,
  85. .device = HM2_PCI_DEV_PLX9054,
  86. - .subvendor = 0x10b5,
  87. + .subvendor = HM2_PCI_VENDORID_PLX,
  88. .subdevice = HM2_PCI_SSDEV_5I22_15,
  89. },
  90.  
  91. // 5i23
  92. {
  93. - .vendor = 0x10b5,
  94. + .vendor = HM2_PCI_VENDORID_PLX,
  95. .device = HM2_PCI_DEV_PLX9054,
  96. - .subvendor = 0x10b5,
  97. + .subvendor = HM2_PCI_VENDORID_PLX,
  98. .subdevice = HM2_PCI_SSDEV_5I23,
  99. },
  100.  
  101. + // 5i25
  102. + {
  103. + .vendor = HM2_PCI_VENDORID_MESA,
  104. + .device = HM2_PCI_DEV_MESA5I25,
  105. + .subvendor = HM2_PCI_VENDORID_MESA,
  106. + .subdevice = HM2_PCI_SSDEV_5I25,
  107. + },
  108. +
  109. // 4i68 (old SSID)
  110. {
  111. - .vendor = 0x10b5,
  112. + .vendor = HM2_PCI_VENDORID_PLX,
  113. .device = HM2_PCI_DEV_PLX9054,
  114. - .subvendor = 0x10b5,
  115. + .subvendor = HM2_PCI_VENDORID_PLX,
  116. .subdevice = HM2_PCI_SSDEV_4I68_OLD,
  117. },
  118.  
  119. // 4i68 (new SSID)
  120. {
  121. - .vendor = 0x10b5,
  122. + .vendor = HM2_PCI_VENDORID_PLX,
  123. .device = HM2_PCI_DEV_PLX9054,
  124. - .subvendor = 0x10b5,
  125. + .subvendor = HM2_PCI_VENDORID_PLX,
  126. .subdevice = HM2_PCI_SSDEV_4I68,
  127. },
  128.  
  129. + // 4i69-16
  130. + {
  131. + .vendor = HM2_PCI_VENDORID_PLX,
  132. + .device = HM2_PCI_DEV_PLX9054,
  133. + .subvendor = HM2_PCI_VENDORID_PLX,
  134. + .subdevice = HM2_PCI_SSDEV_4I69_16,
  135. + },
  136. +
  137. + // 4i69-25
  138. + {
  139. + .vendor = HM2_PCI_VENDORID_PLX,
  140. + .device = HM2_PCI_DEV_PLX9054,
  141. + .subvendor = HM2_PCI_VENDORID_PLX,
  142. + .subdevice = HM2_PCI_SSDEV_4I69_25,
  143. + },
  144. +
  145. // 3X20-1.0M
  146. {
  147. - .vendor = 0x10b5,
  148. + .vendor = HM2_PCI_VENDORID_PLX,
  149. .device = HM2_PCI_DEV_PLX9056,
  150. - .subvendor = 0x10b5,
  151. + .subvendor = HM2_PCI_VENDORID_PLX,
  152. .subdevice = HM2_PCI_SSDEV_3X20_10,
  153. },
  154.  
  155. // 3X20-1.5M
  156. {
  157. - .vendor = 0x10b5,
  158. + .vendor = HM2_PCI_VENDORID_PLX,
  159. .device = HM2_PCI_DEV_PLX9056,
  160. - .subvendor = 0x10b5,
  161. + .subvendor = HM2_PCI_VENDORID_PLX,
  162. .subdevice = HM2_PCI_SSDEV_3X20_15,
  163. },
  164.  
  165. // 3X20-2.0M
  166. {
  167. - .vendor = 0x10b5,
  168. + .vendor = HM2_PCI_VENDORID_PLX,
  169. .device = HM2_PCI_DEV_PLX9056,
  170. - .subvendor = 0x10b5,
  171. + .subvendor = HM2_PCI_VENDORID_PLX,
  172. .subdevice = HM2_PCI_SSDEV_3X20_20,
  173. },
  174.  
  175. @@ -387,6 +422,17 @@ static int hm2_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) {
  176. break;
  177. }
  178.  
  179. + case HM2_PCI_SSDEV_5I21: {
  180. + LL_PRINT("discovered 5i21 at %s\n", pci_name(dev));
  181. + rtapi_snprintf(board->llio.name, sizeof(board->llio.name), "hm2_5i21.%d", num_5i21);
  182. + num_5i21 ++;
  183. + board->llio.num_ioport_connectors = 2;
  184. + board->llio.ioport_connector_name[0] = "P1";
  185. + board->llio.ioport_connector_name[1] = "P1";
  186. + board->llio.fpga_part_number = "3s400pq208";
  187. + break;
  188. + }
  189. +
  190. case HM2_PCI_SSDEV_4I65: {
  191. LL_PRINT("discovered 4i65 at %s\n", pci_name(dev));
  192. rtapi_snprintf(board->llio.name, sizeof(board->llio.name), "hm2_4i65.%d", num_4i65);
  193. @@ -430,6 +476,17 @@ static int hm2_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) {
  194. break;
  195. }
  196.  
  197. + case HM2_PCI_SSDEV_5I25: {
  198. + LL_PRINT("discovered 5i25 at %s\n", pci_name(dev));
  199. + rtapi_snprintf(board->llio.name, sizeof(board->llio.name), "hm2_5i25.%d", num_5i25);
  200. + num_5i25 ++;
  201. + board->llio.num_ioport_connectors = 2;
  202. + board->llio.ioport_connector_name[0] = "P3";
  203. + board->llio.ioport_connector_name[1] = "P2";
  204. + board->llio.fpga_part_number = "6slx9pq144";
  205. + break;
  206. + }
  207. +
  208. case HM2_PCI_SSDEV_4I68:
  209. case HM2_PCI_SSDEV_4I68_OLD: {
  210. if (dev->subsystem_device == HM2_PCI_SSDEV_4I68_OLD) {
  211. @@ -447,6 +504,25 @@ static int hm2_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) {
  212. break;
  213. }
  214.  
  215. + case HM2_PCI_SSDEV_4I69_16:
  216. + case HM2_PCI_SSDEV_4I69_25: {
  217. + if (dev->subsystem_device == HM2_PCI_SSDEV_4I69_16) {
  218. + LL_PRINT("discovered 4I69-16 at %s\n", pci_name(dev));
  219. + board->llio.fpga_part_number = "6slx16fg256";
  220. +
  221. + } else {
  222. + LL_PRINT("discovered 4I69-25 at %s\n", pci_name(dev));
  223. + board->llio.fpga_part_number = "6slx25fg256";
  224. + }
  225. + rtapi_snprintf(board->llio.name, sizeof(board->llio.name), "hm2_4i69.%d", num_4i69);
  226. + num_4i69 ++;
  227. + board->llio.num_ioport_connectors = 3;
  228. + board->llio.ioport_connector_name[0] = "P1";
  229. + board->llio.ioport_connector_name[1] = "P3";
  230. + board->llio.ioport_connector_name[2] = "P4";
  231. + break;
  232. + }
  233. +
  234. case HM2_PCI_SSDEV_3X20_10:
  235. case HM2_PCI_SSDEV_3X20_15:
  236. case HM2_PCI_SSDEV_3X20_20: {
  237. @@ -524,6 +600,18 @@ static int hm2_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) {
  238. break;
  239. }
  240.  
  241. + case HM2_PCI_DEV_MESA5I25: {
  242. + // BAR 0 is 64K mem (32 bit)
  243. + board->len = pci_resource_len(dev, 0);
  244. + board->base = ioremap_nocache(pci_resource_start(dev,0), board->len);
  245. + if (board->base == NULL) {
  246. + THIS_ERR("could not map in FPGA address space\n");
  247. + r = -ENODEV;
  248. + goto fail0;
  249. + }
  250. + break;
  251. + }
  252. +
  253. default: {
  254. THIS_ERR("unknown PCI Device ID 0x%04x\n", dev->device);
  255. r = -ENODEV;
  256. diff --git a/src/hal/drivers/mesa-hostmot2/hm2_pci.h b/src/hal/drivers/mesa-hostmot2/hm2_pci.h
  257. index d25b5d3..b836006 100644
  258. --- a/src/hal/drivers/mesa-hostmot2/hm2_pci.h
  259. +++ b/src/hal/drivers/mesa-hostmot2/hm2_pci.h
  260. @@ -18,7 +18,7 @@
  261. //
  262.  
  263.  
  264. -#define HM2_PCI_VERSION "0.6"
  265. +#define HM2_PCI_VERSION "0.7"
  266.  
  267. #define HM2_LLIO_NAME "hm2_pci"
  268.  
  269. @@ -32,23 +32,33 @@
  270. // PCI Device IDs and SubSystem Device IDs
  271. //
  272.  
  273. +#define HM2_PCI_VENDORID_PLX (0x10B5)
  274. +#define HM2_PCI_VENDORID_MESA (0x2718)
  275. #define HM2_PCI_DEV_PLX9030 (0x9030)
  276. #define HM2_PCI_DEV_PLX9054 (0x9054)
  277. #define HM2_PCI_DEV_PLX9056 (0x9056)
  278.  
  279. +#define HM2_PCI_DEV_MESA5I25 (0x5125)
  280.  
  281. #define HM2_PCI_SSDEV_5I20 (0x3131)
  282.  
  283. #define HM2_PCI_SSDEV_4I65 (0x3132)
  284.  
  285. +#define HM2_PCI_SSDEV_5I21 (0x3312)
  286. +
  287. #define HM2_PCI_SSDEV_5I22_10 (0x3314)
  288. #define HM2_PCI_SSDEV_5I22_15 (0x3313)
  289.  
  290. #define HM2_PCI_SSDEV_5I23 (0x3315)
  291.  
  292. +#define HM2_PCI_SSDEV_5I25 (0x5125)
  293. +
  294. #define HM2_PCI_SSDEV_4I68 (0x3311)
  295. #define HM2_PCI_SSDEV_4I68_OLD (0x3133)
  296.  
  297. +#define HM2_PCI_SSDEV_4I69_16 (0x3472)
  298. +#define HM2_PCI_SSDEV_4I69_25 (0x3473)
  299. +
  300. #define HM2_PCI_SSDEV_3X20_10 (0x3427)
  301. #define HM2_PCI_SSDEV_3X20_15 (0x3428)
  302. #define HM2_PCI_SSDEV_3X20_20 (0x3429)
  303. @@ -94,7 +104,7 @@
  304.  
  305.  
  306. //
  307. -// PLX 9054 (5i22, 5i23, 4i68)
  308. +// PLX 9054 (5i22, 5i23, 4i68, 4i69)
  309. //
  310. // Note: also used for the PLX 9056 (3x20)
  311. //
  312. diff --git a/src/hal/drivers/mesa-hostmot2/hostmot2.c b/src/hal/drivers/mesa-hostmot2/hostmot2.c
  313. index 70f9b3e..bb89341 100644
  314. --- a/src/hal/drivers/mesa-hostmot2/hostmot2.c
  315. +++ b/src/hal/drivers/mesa-hostmot2/hostmot2.c
  316. @@ -320,14 +320,10 @@ static void hm2_print_idrom(hostmot2_t *hm2) {
  317.  
  318. HM2_PRINT(" FPGA Size: %u\n", hm2->idrom.fpga_size);
  319. HM2_PRINT(" FPGA Pins: %u\n", hm2->idrom.fpga_pins);
  320. + HM2_PRINT(" Port Width: %u\n", hm2->idrom.port_width);
  321.  
  322. HM2_PRINT(" IO Ports: %u\n", hm2->idrom.io_ports);
  323. HM2_PRINT(" IO Width: %u\n", hm2->idrom.io_width);
  324. - if (hm2->idrom.port_width == 24) {
  325. - HM2_PRINT(" Port Width: %u\n", hm2->idrom.port_width);
  326. - } else {
  327. - HM2_PRINT(" Port Width: %u ***** Expected 24! Continuing anyway! *****\n", hm2->idrom.port_width);
  328. - }
  329.  
  330. HM2_PRINT(
  331. " Clock Low: %d Hz (%d KHz, %d MHz)\n",
  332. @@ -398,11 +394,6 @@ static int hm2_read_idrom(hostmot2_t *hm2) {
  333. // verify the idrom we read
  334. //
  335.  
  336. - if (hm2->idrom.port_width != 24) {
  337. - HM2_ERR("invalid IDROM PortWidth %d, expected 24, aborting load\n", hm2->idrom.port_width);
  338. - hm2_print_idrom(hm2);
  339. - return -EINVAL;
  340. - }
  341.  
  342. if (hm2->idrom.io_width != (hm2->idrom.io_ports * hm2->idrom.port_width)) {
  343. HM2_ERR(
  344. diff --git a/src/hal/drivers/mesa-hostmot2/pins.c b/src/hal/drivers/mesa-hostmot2/pins.c
  345. index 4e512f7..71f899b 100644
  346. --- a/src/hal/drivers/mesa-hostmot2/pins.c
  347. +++ b/src/hal/drivers/mesa-hostmot2/pins.c
  348. @@ -290,13 +290,39 @@ void hm2_set_pin_direction(hostmot2_t *hm2, int pin_number, int direction) {
  349.  
  350. void hm2_print_pin_usage(hostmot2_t *hm2) {
  351. int i;
  352. + int port, port_pin, mio;
  353.  
  354. HM2_PRINT("%d I/O Pins used:\n", hm2->num_pins);
  355.  
  356. for (i = 0; i < hm2->num_pins; i ++) {
  357. - int port = i / hm2->idrom.port_width;
  358. - int port_pin = ((i % 24) * 2) + 1;
  359. -
  360. + port_pin = i + 1;
  361. + port = i / hm2->idrom.port_width;
  362. + switch (hm2->idrom.port_width) {
  363. + case 24: /* standard 50 pin 24 I/O cards, just the odd pins */
  364. + port_pin = ((i % hm2->idrom.port_width) * 2) + 1;
  365. + break;
  366. + case 17: /* 25 pin 17 I/O parallel port type cards funny DB25 order */
  367. + mio = i % hm2->idrom.port_width;
  368. + if (mio > 7){
  369. + port_pin = mio-3;
  370. + }
  371. + else {
  372. + if (mio & 1){
  373. + port_pin = (mio/2)+14;
  374. + }
  375. + else {
  376. + port_pin = (mio/2)+1;
  377. + }
  378. + }
  379. + break;
  380. + case 32: /* 5I21 punt on this for now */
  381. + port_pin = i+1;
  382. + break;
  383. + default:
  384. + HM2_ERR("hm2_print_pin_usage: invalid port width %d\n", hm2->idrom.port_width);
  385. + }
  386. +
  387. +
  388. if (hm2->pin[i].gtag == hm2->pin[i].sec_tag) {
  389. if(hm2->pin[i].sec_unit & 0x80)
  390. HM2_PRINT(
  391. --
  392. 1.7.0.4
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