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Tyler_Elric

orgate

Sep 20th, 2017
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VHDL 0.29 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4. entity orgate is
  5.     Port ( a : in  STD_LOGIC;
  6.            b : in  STD_LOGIC;
  7.            c : in  STD_LOGIC;
  8.            d : out  STD_LOGIC);
  9. end orgate;
  10.  
  11. architecture Behavioral of orgate is
  12.  
  13. begin
  14.     d <= a or b or c;
  15.  
  16. end Behavioral;
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