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-- Company:
-- Engineer:
--
-- Create Date:    16:05:47 06/19/2010
-- Design Name:
-- Module Name:    CLK_GEN - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CLK_GEN is
    Port ( CLK_IN : in  STD_LOGIC;
           PRESCALE : in  STD_LOGIC_VECTOR (6 downto 0);
           CLK_OUT : out  STD_LOGIC);
end CLK_GEN;

architecture Behavioral of CLK_GEN is
    SIGNAL COUNTER : STD_LOGIC_VECTOR ( 9 downto 0);
    SIGNAL INT_CLK : STD_LOGIC;
begin
    PROCESS ( CLK_IN, COUNTER, PRESCALE )
    BEGIN
        IF RISING_EDGE(CLK_IN) THEN
            COUNTER <= COUNTER + '1';
        END IF;

        IF (COUNTER(9 downto 3) = PRESCALE) THEN
            INT_CLK <= NOT(INT_CLK);
            COUNTER(9 downto 3) <= "0000000";
        END IF;
    END PROCESS;

    CLK_OUT <= INT_CLK;

end Behavioral;