module wb_ram
  #(//Wishbone parameters
     parameter dw = 32,
     // Memory parameters
     parameter depth = 256,
     parameter aw = $clog2(depth))
(input     wb_clk_i,
 input     wb_rst_i,

 input [aw-1:0]  wb_adr_i,
 input [dw-1:0]  wb_dat_i,
 input [3:0]       wb_sel_i,
 input     wb_we_i,
 input [1:0]       wb_bte_i,
 input [2:0]       wb_cti_i,
 input     wb_cyc_i,
 input     wb_stb_i,

 output reg    wb_ack_o,
 output        wb_err_o,
 output        wb_rty_o,
 output [dw-1:0] wb_dat_o);

// Register to address internal memory array
reg [aw-1:0] adr;
wire  [aw-1:0] next_adr;

// Register to indicate if the cycle is a Wishbone B3-registered feedback
// type access
reg                    wb_b3_trans;

wire valid = wb_cyc_i & wb_stb_i;

reg valid_r;

always @(posedge wb_clk_i)
  valid_r <= valid;

// Logic to detect if there's a burst access going on
wire wb_b3_trans_start = ((wb_cti_i == 3'b001)|(wb_cti_i == 3'b010)) &
      valid & !valid_r;

wb_next_adr #(.aw(aw)) wb_next_adr0(adr, wb_cti_i, wb_bte_i, next_adr);

wire burst_access_wrong_wb_adr = 1'b0;

// Address registering logic
always@(posedge wb_clk_i)
  if(wb_rst_i)
     adr <= 0;
  else if (valid & wb_ack_o)
     adr <= next_adr;
  else if(valid & !valid_r)
     adr <= wb_adr_i;

assign wb_rty_o = 0;

wire ram_we = wb_we_i & valid & wb_ack_o;

// Ack Logic
reg wb_ack_o_r;

always @(posedge wb_clk_i)
  wb_ack_o <= valid & (!((wb_cti_i == 3'b000) | (wb_cti_i == 3'b111)) | !wb_ack_o);

//
// Error signal generation
//

// OR in other errors here...
assign wb_err_o =  1'b0; //wb_ack_o_r & wb_stb_i &
//(burst_access_wrong_wb_adr);


wb_ram_generic
  #(.aw (aw),
     .depth(depth))
ram0
  (.clk (wb_clk_i),
   .we  ({4{ram_we}} & wb_sel_i),
   .din (wb_dat_i),
   .addr (ram_we ? adr : wb_b3_trans_start ? wb_adr_i : next_adr),
   .dout (wb_dat_o));

endmodule