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Jul 7th, 2015
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  1. wire [511:0] data_mem0 = mem[x1];
  2. wire [511:0] data_mem1 = mem[x2];
  3. wire [31:0] sparse_bits = {data_mem0[7:0],data_mem1[7:0],data_mem0[511:504],data_mem1[511:504]};
  4.  
  5. module mem_if(
  6. addr,
  7. rw,
  8. din,
  9. dout,
  10. clk,
  11. rst_
  12. );
  13. input [6:0] addr;
  14. input rw;
  15. input [511:0] din;
  16. output [511:0] dout;
  17. input clk;
  18. input rst_;
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