Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- wire [511:0] data_mem0 = mem[x1];
- wire [511:0] data_mem1 = mem[x2];
- wire [31:0] sparse_bits = {data_mem0[7:0],data_mem1[7:0],data_mem0[511:504],data_mem1[511:504]};
- module mem_if(
- addr,
- rw,
- din,
- dout,
- clk,
- rst_
- );
- input [6:0] addr;
- input rw;
- input [511:0] din;
- output [511:0] dout;
- input clk;
- input rst_;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement