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Jan 4th, 2017
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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x1>;
  5. #size-cells = <0x1>;
  6. model = "MSC nanoRISC i.MX6DL";
  7. compatible = "msc,imx6dl_nanoRISC", "fsl,imx6dl";
  8.  
  9. chosen {
  10. };
  11.  
  12. aliases {
  13. flexcan0 = "/soc/aips-bus@02000000/can@02090000";
  14. flexcan1 = "/soc/aips-bus@02000000/can@02094000";
  15. gpio0 = "/soc/aips-bus@02000000/gpio@0209c000";
  16. gpio1 = "/soc/aips-bus@02000000/gpio@020a0000";
  17. gpio2 = "/soc/aips-bus@02000000/gpio@020a4000";
  18. gpio3 = "/soc/aips-bus@02000000/gpio@020a8000";
  19. gpio4 = "/soc/aips-bus@02000000/gpio@020ac000";
  20. gpio5 = "/soc/aips-bus@02000000/gpio@020b0000";
  21. gpio6 = "/soc/aips-bus@02000000/gpio@020b4000";
  22. ipu0 = "/soc/ipu@02400000";
  23. serial0 = "/soc/aips-bus@02000000/spba-bus@02000000/serial@02020000";
  24. serial1 = "/soc/aips-bus@02100000/serial@021e8000";
  25. serial2 = "/soc/aips-bus@02100000/serial@021ec000";
  26. serial3 = "/soc/aips-bus@02100000/serial@021f0000";
  27. serial4 = "/soc/aips-bus@02100000/serial@021f4000";
  28. usbphy0 = "/soc/aips-bus@02000000/usbphy@020c9000";
  29. usbphy1 = "/soc/aips-bus@02000000/usbphy@020ca000";
  30. mxcfb0 = "/fb@0";
  31. };
  32.  
  33. memory {
  34. device_type = "memory";
  35. reg = <0x10000000 0x40000000>;
  36. };
  37.  
  38. interrupt-controller@00a01000 {
  39. compatible = "arm,cortex-a9-gic";
  40. #interrupt-cells = <0x3>;
  41. #address-cells = <0x1>;
  42. #size-cells = <0x1>;
  43. interrupt-controller;
  44. reg = <0xa01000 0x1000 0xa00100 0x100>;
  45. linux,phandle = <0x1>;
  46. phandle = <0x1>;
  47. };
  48.  
  49. clocks {
  50. #address-cells = <0x1>;
  51. #size-cells = <0x0>;
  52.  
  53. ckil {
  54. compatible = "fsl,imx-ckil", "fixed-clock";
  55. clock-frequency = <0x8000>;
  56. };
  57.  
  58. ckih1 {
  59. compatible = "fsl,imx-ckih1", "fixed-clock";
  60. clock-frequency = <0x0>;
  61. };
  62.  
  63. osc {
  64. compatible = "fsl,imx-osc", "fixed-clock";
  65. clock-frequency = <0x16e3600>;
  66. };
  67. };
  68.  
  69. pudummy_reg {
  70. compatible = "fsl,imx6-dummy-pureg";
  71. };
  72.  
  73. mxs_viim {
  74. compatible = "fsl,mxs_viim";
  75. reg = <0x2098000 0x1000 0x21bc000 0x1000>;
  76. };
  77.  
  78. soc {
  79. #address-cells = <0x1>;
  80. #size-cells = <0x1>;
  81. compatible = "simple-bus";
  82. interrupt-parent = <0x1>;
  83. ranges;
  84.  
  85. caam-sm@00100000 {
  86. compatible = "fsl,imx6q-caam-sm";
  87. reg = <0x100000 0x3fff>;
  88. };
  89.  
  90. dma-apbh@00110000 {
  91. compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  92. reg = <0x110000 0x2000>;
  93. interrupts = <0x0 0xd 0x4 0x0 0xd 0x4 0x0 0xd 0x4 0x0 0xd 0x4>;
  94. interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  95. #dma-cells = <0x1>;
  96. dma-channels = <0x4>;
  97. clocks = <0x2 0x6a>;
  98. linux,phandle = <0x3>;
  99. phandle = <0x3>;
  100. };
  101.  
  102. caam_secvio {
  103. compatible = "fsl,imx6q-caam-secvio";
  104. interrupts = <0x0 0x14 0x4>;
  105. secvio_src = <0x8000001d>;
  106. };
  107.  
  108. gpmi-nand@00112000 {
  109. compatible = "fsl,imx6q-gpmi-nand";
  110. #address-cells = <0x1>;
  111. #size-cells = <0x1>;
  112. reg = <0x112000 0x2000 0x114000 0x2000>;
  113. reg-names = "gpmi-nand", "bch";
  114. interrupts = <0x0 0xf 0x4>;
  115. interrupt-names = "bch";
  116. clocks = <0x2 0x98 0x2 0x99 0x2 0x97 0x2 0x96 0x2 0x95>;
  117. clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_bch_apb", "per1_bch";
  118. dmas = <0x3 0x0>;
  119. dma-names = "rx-tx";
  120. status = "okay";
  121. pinctrl-names = "default";
  122. pinctrl-0 = <0x4>;
  123. nand-on-flash-bbt;
  124. };
  125.  
  126. timer@00a00600 {
  127. compatible = "arm,cortex-a9-twd-timer";
  128. reg = <0xa00600 0x20>;
  129. interrupts = <0x1 0xd 0xf01>;
  130. clocks = <0x2 0xf>;
  131. };
  132.  
  133. l2-cache@00a02000 {
  134. compatible = "arm,pl310-cache";
  135. reg = <0xa02000 0x1000>;
  136. interrupts = <0x0 0x5c 0x4>;
  137. cache-unified;
  138. cache-level = <0x2>;
  139. arm,tag-latency = <0x4 0x2 0x3>;
  140. arm,data-latency = <0x4 0x2 0x3>;
  141. linux,phandle = <0x2d>;
  142. phandle = <0x2d>;
  143. };
  144.  
  145. pcie@0x01000000 {
  146. compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
  147. reg = <0x1ffc000 0x4000>;
  148. #address-cells = <0x3>;
  149. #size-cells = <0x2>;
  150. device_type = "pci";
  151. ranges = <0x800 0x0 0x1f00000 0x1f00000 0x0 0x80000 0x81000000 0x0 0x0 0x1f80000 0x0 0x10000 0x82000000 0x0 0x1000000 0x1000000 0x0 0xf00000>;
  152. num-lanes = <0x1>;
  153. interrupts = <0x0 0x7b 0x4>;
  154. clocks = <0x2 0xbd 0x2 0xbb 0x2 0x90 0x2 0xd4>;
  155. clock-names = "pcie_ref_125m", "sata_ref_100m", "pcie_axi", "lvds_gate";
  156. status = "okay";
  157. reset-gpio = <0x5 0x1a 0x0>;
  158. };
  159.  
  160. pmu {
  161. compatible = "arm,cortex-a9-pmu";
  162. interrupts = <0x0 0x5e 0x4>;
  163. };
  164.  
  165. aips-bus@02000000 {
  166. compatible = "fsl,aips-bus", "simple-bus";
  167. #address-cells = <0x1>;
  168. #size-cells = <0x1>;
  169. reg = <0x2000000 0x100000>;
  170. ranges;
  171.  
  172. spba-bus@02000000 {
  173. compatible = "fsl,spba-bus", "simple-bus";
  174. #address-cells = <0x1>;
  175. #size-cells = <0x1>;
  176. reg = <0x2000000 0x40000>;
  177. ranges;
  178.  
  179. spdif@02004000 {
  180. compatible = "fsl,imx6q-spdif", "fsl,imx35-spdif";
  181. reg = <0x2004000 0x4000>;
  182. interrupts = <0x0 0x34 0x4>;
  183. dmas = <0x6 0xe 0x12 0x0 0x6 0xf 0x12 0x0>;
  184. dma-names = "rx", "tx";
  185. clocks = <0x2 0xc5 0x2 0x3 0x2 0xc5 0x2 0x6b 0x2 0x0 0x2 0x76 0x2 0x3e 0x2 0x8b 0x2 0x0 0x2 0x9c>;
  186. clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", "rxtx5", "rxtx6", "rxtx7", "dma";
  187. status = "disabled";
  188. };
  189.  
  190. ecspi@02008000 {
  191. #address-cells = <0x1>;
  192. #size-cells = <0x0>;
  193. compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  194. reg = <0x2008000 0x4000>;
  195. interrupts = <0x0 0x1f 0x4>;
  196. clocks = <0x2 0x70 0x2 0x70>;
  197. clock-names = "ipg", "per";
  198. status = "okay";
  199. fsl,spi-num-chipselects = <0x1>;
  200. cs-gpios = <0x0>;
  201. pinctrl-names = "default";
  202. pinctrl-0 = <0x7>;
  203.  
  204. spidev@0 {
  205. compatible = "spidev";
  206. spi-max-frequency = <0x186a0>;
  207. reg = <0x0>;
  208. };
  209. };
  210.  
  211. ecspi@0200c000 {
  212. #address-cells = <0x1>;
  213. #size-cells = <0x0>;
  214. compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  215. reg = <0x200c000 0x4000>;
  216. interrupts = <0x0 0x20 0x4>;
  217. clocks = <0x2 0x71 0x2 0x71>;
  218. clock-names = "ipg", "per";
  219. status = "disabled";
  220. };
  221.  
  222. ecspi@02010000 {
  223. #address-cells = <0x1>;
  224. #size-cells = <0x0>;
  225. compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  226. reg = <0x2010000 0x4000>;
  227. interrupts = <0x0 0x21 0x4>;
  228. clocks = <0x2 0x72 0x2 0x72>;
  229. clock-names = "ipg", "per";
  230. status = "disabled";
  231. };
  232.  
  233. ecspi@02014000 {
  234. #address-cells = <0x1>;
  235. #size-cells = <0x0>;
  236. compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  237. reg = <0x2014000 0x4000>;
  238. interrupts = <0x0 0x22 0x4>;
  239. clocks = <0x2 0x73 0x2 0x73>;
  240. clock-names = "ipg", "per";
  241. status = "okay";
  242. fsl,spi-num-chipselects = <0x1>;
  243. cs-gpios = <0x8 0x2 0x0>;
  244. pinctrl-names = "default";
  245. pinctrl-0 = <0x9>;
  246.  
  247. m25@0 {
  248. #address-cells = <0x1>;
  249. #size-cells = <0x1>;
  250. compatible = "m25p16";
  251. spi-max-frequency = <0x2faf080>;
  252. reg = <0x0>;
  253.  
  254. partition@0 {
  255. label = "SPL";
  256. reg = <0x0 0x20000>;
  257. };
  258.  
  259. partition@20000 {
  260. label = "env";
  261. reg = <0x20000 0x20000>;
  262. };
  263.  
  264. partition@40000 {
  265. label = "uboot";
  266. reg = <0x40000 0x80000>;
  267. };
  268.  
  269. partition@c0000 {
  270. label = "user";
  271. reg = <0xc0000 0x0>;
  272. };
  273. };
  274. };
  275.  
  276. serial@02020000 {
  277. compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
  278. reg = <0x2020000 0x4000>;
  279. interrupts = <0x0 0x1a 0x4>;
  280. clocks = <0x2 0xa0 0x2 0xa1>;
  281. clock-names = "ipg", "per";
  282. dmas = <0x6 0x19 0x4 0x0 0x6 0x1a 0x4 0x0>;
  283. dma-names = "rx", "tx";
  284. status = "okay";
  285. pinctrl-names = "default";
  286. pinctrl-0 = <0xa>;
  287. fsl,uart-has-rtscts;
  288. };
  289.  
  290. esai@02024000 {
  291. compatible = "fsl,imx6q-esai";
  292. reg = <0x2024000 0x4000>;
  293. interrupts = <0x0 0x33 0x4>;
  294. clocks = <0x2 0x76 0x2 0x9c>;
  295. clock-names = "core", "dma";
  296. fsl,esai-dma-events = <0x18 0x17>;
  297. fsl,flags = <0x1>;
  298. status = "disabled";
  299. };
  300.  
  301. ssi@02028000 {
  302. compatible = "fsl,imx6q-ssi", "fsl,imx21-ssi";
  303. reg = <0x2028000 0x4000>;
  304. interrupts = <0x0 0x2e 0x4>;
  305. clocks = <0x2 0xb2 0x2 0x9d>;
  306. clock-names = "ipg", "baud";
  307. dmas = <0x6 0x25 0x1 0x0 0x6 0x26 0x1 0x0>;
  308. dma-names = "rx", "tx";
  309. status = "okay";
  310. fsl,mode = "i2s-slave";
  311. linux,phandle = <0x34>;
  312. phandle = <0x34>;
  313. };
  314.  
  315. ssi@0202c000 {
  316. compatible = "fsl,imx6q-ssi", "fsl,imx21-ssi";
  317. reg = <0x202c000 0x4000>;
  318. interrupts = <0x0 0x2f 0x4>;
  319. clocks = <0x2 0xb3 0x2 0x9e>;
  320. clock-names = "ipg", "baud";
  321. dmas = <0x6 0x29 0x1 0x0 0x6 0x2a 0x1 0x0>;
  322. dma-names = "rx", "tx";
  323. status = "okay";
  324. fsl,mode = "i2s-slave";
  325. };
  326.  
  327. ssi@02030000 {
  328. compatible = "fsl,imx6q-ssi", "fsl,imx21-ssi";
  329. reg = <0x2030000 0x4000>;
  330. interrupts = <0x0 0x30 0x4>;
  331. clocks = <0x2 0xb4 0x2 0x9f>;
  332. clock-names = "ipg", "baud";
  333. dmas = <0x6 0x2d 0x1 0x0 0x6 0x2e 0x1 0x0>;
  334. dma-names = "rx", "tx";
  335. status = "disabled";
  336. };
  337.  
  338. asrc@02034000 {
  339. compatible = "fsl,imx53-asrc";
  340. reg = <0x2034000 0x4000>;
  341. interrupts = <0x0 0x32 0x4>;
  342. clocks = <0x2 0x6b 0x2 0x9c>;
  343. clock-names = "core", "dma";
  344. dmas = <0x6 0x11 0x14 0x1 0x6 0x12 0x14 0x1 0x6 0x13 0x14 0x1 0x6 0x14 0x14 0x1 0x6 0x15 0x14 0x1 0x6 0x16 0x14 0x1>;
  345. dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
  346. status = "okay";
  347. };
  348.  
  349. asrc_p2p {
  350. compatible = "fsl,imx6q-asrc-p2p";
  351. fsl,output-rate = <0xbb80>;
  352. fsl,output-width = <0x10>;
  353. fsl,asrc-dma-rx-events = <0x11 0x12 0x13>;
  354. fsl,asrc-dma-tx-events = <0x14 0x15 0x16>;
  355. status = "okay";
  356. };
  357.  
  358. spba@0203c000 {
  359. reg = <0x203c000 0x4000>;
  360. };
  361. };
  362.  
  363. vpu@02040000 {
  364. compatible = "fsl,imx6-vpu";
  365. reg = <0x2040000 0x3c000>;
  366. reg-names = "vpu_regs";
  367. interrupts = <0x0 0x3 0x1 0x0 0xc 0x4>;
  368. interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq";
  369. clocks = <0x2 0xa8 0x2 0x8c 0x2 0x8e>;
  370. clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
  371. iramsize = <0x0>;
  372. iram = <0xb>;
  373. resets = <0xc 0x1>;
  374. pu-supply = <0xd>;
  375. status = "okay";
  376. };
  377.  
  378. aipstz@0207c000 {
  379. reg = <0x207c000 0x4000>;
  380. };
  381.  
  382. pwm@02080000 {
  383. #pwm-cells = <0x2>;
  384. compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
  385. reg = <0x2080000 0x4000>;
  386. interrupts = <0x0 0x53 0x4>;
  387. clocks = <0x2 0x3e 0x2 0x91>;
  388. clock-names = "ipg", "per";
  389. pinctrl-names = "default";
  390. pinctrl-0 = <0xe>;
  391. status = "okay";
  392. linux,phandle = <0x37>;
  393. phandle = <0x37>;
  394. };
  395.  
  396. pwm@02084000 {
  397. #pwm-cells = <0x2>;
  398. compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
  399. reg = <0x2084000 0x4000>;
  400. interrupts = <0x0 0x54 0x4>;
  401. clocks = <0x2 0x3e 0x2 0x92>;
  402. clock-names = "ipg", "per";
  403. };
  404.  
  405. pwm@02088000 {
  406. #pwm-cells = <0x2>;
  407. compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
  408. reg = <0x2088000 0x4000>;
  409. interrupts = <0x0 0x55 0x4>;
  410. clocks = <0x2 0x3e 0x2 0x93>;
  411. clock-names = "ipg", "per";
  412. };
  413.  
  414. pwm@0208c000 {
  415. #pwm-cells = <0x2>;
  416. compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
  417. reg = <0x208c000 0x4000>;
  418. interrupts = <0x0 0x56 0x4>;
  419. clocks = <0x2 0x3e 0x2 0x94>;
  420. clock-names = "ipg", "per";
  421. };
  422.  
  423. can@02090000 {
  424. compatible = "fsl,imx6q-flexcan";
  425. reg = <0x2090000 0x4000>;
  426. interrupts = <0x0 0x6e 0x4>;
  427. clocks = <0x2 0x6c 0x2 0x6d>;
  428. clock-names = "ipg", "per";
  429. gpr = <0xf>;
  430. status = "okay";
  431. pinctrl-names = "default";
  432. pinctrl-0 = <0x10>;
  433. };
  434.  
  435. can@02094000 {
  436. compatible = "fsl,imx6q-flexcan";
  437. reg = <0x2094000 0x4000>;
  438. interrupts = <0x0 0x6f 0x4>;
  439. clocks = <0x2 0x6e 0x2 0x6f>;
  440. clock-names = "ipg", "per";
  441. gpr = <0xf>;
  442. status = "disabled";
  443. };
  444.  
  445. gpt@02098000 {
  446. compatible = "fsl,imx6q-gpt";
  447. reg = <0x2098000 0x4000>;
  448. interrupts = <0x0 0x37 0x4>;
  449. clocks = <0x2 0x77 0x2 0x78>;
  450. clock-names = "ipg", "per";
  451. };
  452.  
  453. gpio@0209c000 {
  454. compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
  455. reg = <0x209c000 0x4000>;
  456. interrupts = <0x0 0x42 0x4 0x0 0x43 0x4>;
  457. gpio-controller;
  458. #gpio-cells = <0x2>;
  459. interrupt-controller;
  460. #interrupt-cells = <0x2>;
  461. linux,phandle = <0x5>;
  462. phandle = <0x5>;
  463. };
  464.  
  465. gpio@020a0000 {
  466. compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
  467. reg = <0x20a0000 0x4000>;
  468. interrupts = <0x0 0x44 0x4 0x0 0x45 0x4>;
  469. gpio-controller;
  470. #gpio-cells = <0x2>;
  471. interrupt-controller;
  472. #interrupt-cells = <0x2>;
  473. linux,phandle = <0x31>;
  474. phandle = <0x31>;
  475. };
  476.  
  477. gpio@020a4000 {
  478. compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
  479. reg = <0x20a4000 0x4000>;
  480. interrupts = <0x0 0x46 0x4 0x0 0x47 0x4>;
  481. gpio-controller;
  482. #gpio-cells = <0x2>;
  483. interrupt-controller;
  484. #interrupt-cells = <0x2>;
  485. linux,phandle = <0x32>;
  486. phandle = <0x32>;
  487. };
  488.  
  489. gpio@020a8000 {
  490. compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
  491. reg = <0x20a8000 0x4000>;
  492. interrupts = <0x0 0x48 0x4 0x0 0x49 0x4>;
  493. gpio-controller;
  494. #gpio-cells = <0x2>;
  495. interrupt-controller;
  496. #interrupt-cells = <0x2>;
  497. linux,phandle = <0x1f>;
  498. phandle = <0x1f>;
  499. };
  500.  
  501. gpio@020ac000 {
  502. compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
  503. reg = <0x20ac000 0x4000>;
  504. interrupts = <0x0 0x4a 0x4 0x0 0x4b 0x4>;
  505. gpio-controller;
  506. #gpio-cells = <0x2>;
  507. interrupt-controller;
  508. #interrupt-cells = <0x2>;
  509. linux,phandle = <0x8>;
  510. phandle = <0x8>;
  511. };
  512.  
  513. gpio@020b0000 {
  514. compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
  515. reg = <0x20b0000 0x4000>;
  516. interrupts = <0x0 0x4c 0x4 0x0 0x4d 0x4>;
  517. gpio-controller;
  518. #gpio-cells = <0x2>;
  519. interrupt-controller;
  520. #interrupt-cells = <0x2>;
  521. linux,phandle = <0x33>;
  522. phandle = <0x33>;
  523. };
  524.  
  525. gpio@020b4000 {
  526. compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
  527. reg = <0x20b4000 0x4000>;
  528. interrupts = <0x0 0x4e 0x4 0x0 0x4f 0x4>;
  529. gpio-controller;
  530. #gpio-cells = <0x2>;
  531. interrupt-controller;
  532. #interrupt-cells = <0x2>;
  533. linux,phandle = <0x21>;
  534. phandle = <0x21>;
  535. };
  536.  
  537. kpp@020b8000 {
  538. reg = <0x20b8000 0x4000>;
  539. interrupts = <0x0 0x52 0x4>;
  540. };
  541.  
  542. wdog@020bc000 {
  543. compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
  544. reg = <0x20bc000 0x4000>;
  545. interrupts = <0x0 0x50 0x4>;
  546. clocks = <0x2 0x0>;
  547. };
  548.  
  549. wdog@020c0000 {
  550. compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
  551. reg = <0x20c0000 0x4000>;
  552. interrupts = <0x0 0x51 0x4>;
  553. clocks = <0x2 0x0>;
  554. status = "disabled";
  555. };
  556.  
  557. ccm@020c4000 {
  558. compatible = "fsl,imx6q-ccm";
  559. reg = <0x20c4000 0x4000>;
  560. interrupts = <0x0 0x57 0x4 0x0 0x58 0x4>;
  561. #clock-cells = <0x1>;
  562. linux,phandle = <0x2>;
  563. phandle = <0x2>;
  564. };
  565.  
  566. anatop@020c8000 {
  567. compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
  568. reg = <0x20c8000 0x1000>;
  569. interrupts = <0x0 0x31 0x4 0x0 0x36 0x4 0x0 0x7f 0x4>;
  570. linux,phandle = <0x11>;
  571. phandle = <0x11>;
  572.  
  573. regulator-1p1@110 {
  574. compatible = "fsl,anatop-regulator";
  575. regulator-name = "vdd1p1";
  576. regulator-min-microvolt = <0xc3500>;
  577. regulator-max-microvolt = <0x14fb18>;
  578. regulator-always-on;
  579. anatop-reg-offset = <0x110>;
  580. anatop-vol-bit-shift = <0x8>;
  581. anatop-vol-bit-width = <0x5>;
  582. anatop-min-bit-val = <0x4>;
  583. anatop-min-voltage = <0xc3500>;
  584. anatop-max-voltage = <0x14fb18>;
  585. };
  586.  
  587. regulator-3p0@120 {
  588. compatible = "fsl,anatop-regulator";
  589. regulator-name = "vdd3p0";
  590. regulator-min-microvolt = <0x2ab980>;
  591. regulator-max-microvolt = <0x3010b0>;
  592. regulator-always-on;
  593. anatop-reg-offset = <0x120>;
  594. anatop-vol-bit-shift = <0x8>;
  595. anatop-vol-bit-width = <0x5>;
  596. anatop-min-bit-val = <0x0>;
  597. anatop-min-voltage = <0x280de8>;
  598. anatop-max-voltage = <0x33e140>;
  599. };
  600.  
  601. regulator-2p5@130 {
  602. compatible = "fsl,anatop-regulator";
  603. regulator-name = "vdd2p5";
  604. regulator-min-microvolt = <0x1e8480>;
  605. regulator-max-microvolt = <0x29f630>;
  606. regulator-always-on;
  607. anatop-reg-offset = <0x130>;
  608. anatop-vol-bit-shift = <0x8>;
  609. anatop-vol-bit-width = <0x5>;
  610. anatop-min-bit-val = <0x0>;
  611. anatop-min-voltage = <0x1e8480>;
  612. anatop-max-voltage = <0x29f630>;
  613. };
  614.  
  615. regulator-vddcore@140 {
  616. compatible = "fsl,anatop-regulator";
  617. regulator-name = "cpu";
  618. regulator-min-microvolt = <0xb1008>;
  619. regulator-max-microvolt = <0x162010>;
  620. regulator-always-on;
  621. anatop-reg-offset = <0x140>;
  622. anatop-vol-bit-shift = <0x0>;
  623. anatop-vol-bit-width = <0x5>;
  624. anatop-delay-reg-offset = <0x170>;
  625. anatop-delay-bit-shift = <0x18>;
  626. anatop-delay-bit-width = <0x2>;
  627. anatop-min-bit-val = <0x1>;
  628. anatop-min-voltage = <0xb1008>;
  629. anatop-max-voltage = <0x162010>;
  630. linux,phandle = <0x2e>;
  631. phandle = <0x2e>;
  632. };
  633.  
  634. regulator-vddpu@140 {
  635. compatible = "fsl,anatop-regulator";
  636. regulator-name = "vddpu";
  637. regulator-min-microvolt = <0xb1008>;
  638. regulator-max-microvolt = <0x162010>;
  639. anatop-reg-offset = <0x140>;
  640. anatop-vol-bit-shift = <0x9>;
  641. anatop-vol-bit-width = <0x5>;
  642. anatop-delay-reg-offset = <0x170>;
  643. anatop-delay-bit-shift = <0x1a>;
  644. anatop-delay-bit-width = <0x2>;
  645. anatop-min-bit-val = <0x1>;
  646. anatop-min-voltage = <0xb1008>;
  647. anatop-max-voltage = <0x162010>;
  648. linux,phandle = <0xd>;
  649. phandle = <0xd>;
  650. };
  651.  
  652. regulator-vddsoc@140 {
  653. compatible = "fsl,anatop-regulator";
  654. regulator-name = "vddsoc";
  655. regulator-min-microvolt = <0xb1008>;
  656. regulator-max-microvolt = <0x162010>;
  657. regulator-always-on;
  658. anatop-reg-offset = <0x140>;
  659. anatop-vol-bit-shift = <0x12>;
  660. anatop-vol-bit-width = <0x5>;
  661. anatop-delay-reg-offset = <0x170>;
  662. anatop-delay-bit-shift = <0x1c>;
  663. anatop-delay-bit-width = <0x2>;
  664. anatop-min-bit-val = <0x1>;
  665. anatop-min-voltage = <0xb1008>;
  666. anatop-max-voltage = <0x162010>;
  667. linux,phandle = <0x2f>;
  668. phandle = <0x2f>;
  669. };
  670. };
  671.  
  672. tempmon {
  673. compatible = "fsl,imx6q-tempmon";
  674. interrupts = <0x0 0x31 0x4>;
  675. fsl,tempmon = <0x11>;
  676. fsl,tempmon-data = <0x12>;
  677. clocks = <0x2 0xac>;
  678. };
  679.  
  680. usbphy@020c9000 {
  681. compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
  682. reg = <0x20c9000 0x1000>;
  683. interrupts = <0x0 0x2c 0x4>;
  684. clocks = <0x2 0xb6>;
  685. fsl,anatop = <0x11>;
  686. linux,phandle = <0x14>;
  687. phandle = <0x14>;
  688. };
  689.  
  690. usbphy@020ca000 {
  691. compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
  692. reg = <0x20ca000 0x1000>;
  693. interrupts = <0x0 0x2d 0x4>;
  694. clocks = <0x2 0xb7>;
  695. fsl,anatop = <0x11>;
  696. linux,phandle = <0x18>;
  697. phandle = <0x18>;
  698. };
  699.  
  700. usbphy_nop1 {
  701. compatible = "usb-nop-xceiv";
  702. clocks = <0x2 0xb6>;
  703. clock-names = "main_clk";
  704. linux,phandle = <0x1a>;
  705. phandle = <0x1a>;
  706. };
  707.  
  708. usbphy_nop2 {
  709. compatible = "usb-nop-xceiv";
  710. clocks = <0x2 0xb6>;
  711. clock-names = "main_clk";
  712. linux,phandle = <0x1b>;
  713. phandle = <0x1b>;
  714. };
  715.  
  716. caam-snvs@020cc000 {
  717. compatible = "fsl,imx6q-caam-snvs";
  718. reg = <0x20cc000 0x4000>;
  719. };
  720.  
  721. snvs@020cc000 {
  722. compatible = "fsl,sec-v4.0-mon", "simple-bus";
  723. #address-cells = <0x1>;
  724. #size-cells = <0x1>;
  725. ranges = <0x0 0x20cc000 0x4000>;
  726.  
  727. snvs-rtc-lp@34 {
  728. compatible = "fsl,sec-v4.0-mon-rtc-lp";
  729. reg = <0x34 0x58>;
  730. interrupts = <0x0 0x13 0x4 0x0 0x14 0x4>;
  731. };
  732. };
  733.  
  734. epit@020d0000 {
  735. reg = <0x20d0000 0x4000>;
  736. interrupts = <0x0 0x38 0x4>;
  737. };
  738.  
  739. epit@020d4000 {
  740. reg = <0x20d4000 0x4000>;
  741. interrupts = <0x0 0x39 0x4>;
  742. };
  743.  
  744. src@020d8000 {
  745. compatible = "fsl,imx6q-src", "fsl,imx51-src";
  746. reg = <0x20d8000 0x4000>;
  747. interrupts = <0x0 0x5b 0x4 0x0 0x60 0x4>;
  748. #reset-cells = <0x1>;
  749. linux,phandle = <0xc>;
  750. phandle = <0xc>;
  751. };
  752.  
  753. gpc@020dc000 {
  754. compatible = "fsl,imx6q-gpc";
  755. reg = <0x20dc000 0x4000>;
  756. interrupts = <0x0 0x59 0x4 0x0 0x5a 0x4>;
  757. clocks = <0x2 0x7a 0x2 0x4a 0x2 0x79 0x2 0x1a 0x2 0x8f 0x2 0xa8 0x2 0x3e>;
  758. clock-names = "gpu3d_core", "gpu3d_shader", "gpu2d_core", "gpu2d_axi", "openvg_axi", "vpu_axi", "ipg";
  759. pu-supply = <0xd>;
  760. fsl,cpu_pupscr_sw2iso = <0xf>;
  761. fsl,cpu_pupscr_sw = <0xf>;
  762. fsl,cpu_pdnscr_iso2sw = <0x1>;
  763. fsl,cpu_pdnscr_iso = <0x1>;
  764. fsl,ldo-bypass = <0x0>;
  765. fsl,wdog-reset = <0x1>;
  766. };
  767.  
  768. iomuxc-gpr@020e0000 {
  769. compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
  770. reg = <0x20e0000 0x38>;
  771. linux,phandle = <0xf>;
  772. phandle = <0xf>;
  773. };
  774.  
  775. iomuxc@020e0000 {
  776. reg = <0x20e0000 0x4000>;
  777. compatible = "fsl,imx6dl-iomuxc";
  778. pinctrl-names = "default";
  779. pinctrl-0 = <0x13>;
  780.  
  781. audmux {
  782.  
  783. audmux-1 {
  784. fsl,pins = <0x2fc 0x6e4 0x798 0x3 0x1 0x130b0 0x308 0x6f0 0x7a8 0x3 0x1 0x130b0 0x304 0x6ec 0x79c 0x3 0x1 0x110b0 0x300 0x6e8 0x7ac 0x3 0x1 0x130b0>;
  785. };
  786.  
  787. audmux-2 {
  788. fsl,pins = <0x80 0x394 0x0 0x4 0x0 0x130b0 0x74 0x388 0x0 0x4 0x0 0x130b0 0x78 0x38c 0x0 0x4 0x0 0x110b0 0x7c 0x390 0x0 0x4 0x0 0x130b0>;
  789. linux,phandle = <0x29>;
  790. phandle = <0x29>;
  791. };
  792.  
  793. audmux-3 {
  794. fsl,pins = <0xd0 0x3e4 0x7c0 0x3 0x0 0x130b0 0xd8 0x3ec 0x7c4 0x3 0x0 0x130b0 0xdc 0x3f0 0x7b0 0x3 0x0 0x130b0>;
  795. };
  796. };
  797.  
  798. ecspi1 {
  799.  
  800. ecspi1_cs_grp-1 {
  801. fsl,pins = <0x150 0x520 0x0 0x5 0x0 0x80000000>;
  802. };
  803.  
  804. ecspi1grp-1 {
  805. fsl,pins = <0x248 0x630 0x7dc 0x0 0x3 0x100b1 0x258 0x640 0x7e0 0x0 0x3 0x100b1 0x244 0x62c 0x7d8 0x0 0x3 0x100b1 0x25c 0x644 0x7e4 0x0 0x3 0x100b1>;
  806. linux,phandle = <0x7>;
  807. phandle = <0x7>;
  808. };
  809.  
  810. ecspi1grp-2 {
  811. fsl,pins = <0x248 0x630 0x7dc 0x0 0x3 0x100b1 0x258 0x640 0x7e0 0x0 0x3 0x100b1 0x244 0x62c 0x7d8 0x0 0x3 0x100b1>;
  812. };
  813. };
  814.  
  815. ecspi3 {
  816.  
  817. ecspi3grp-1 {
  818. fsl,pins = <0xe0 0x3f4 0x0 0x2 0x0 0x100b1 0xb4 0x3c8 0x0 0x2 0x0 0x100b1 0xb0 0x3c4 0x0 0x2 0x0 0x100b1>;
  819. };
  820. };
  821.  
  822. enet {
  823.  
  824. enetgrp-1 {
  825. fsl,pins = <0x1ec 0x5bc 0x810 0x1 0x0 0x1b0b0 0x1e8 0x5b8 0x0 0x1 0x0 0x1b0b0 0x2d8 0x6c0 0x0 0x1 0x0 0x1b0b0 0x2c4 0x6ac 0x0 0x1 0x0 0x1b0b0 0x2c8 0x6b0 0x0 0x1 0x0 0x1b0b0 0x2cc 0x6b4 0x0 0x1 0x0 0x1b0b0 0x2d0 0x6b8 0x0 0x1 0x0 0x1b0b0 0x2d4 0x6bc 0x0 0x1 0x0 0x1b0b0 0x1f0 0x5c0 0x0 0x1 0x0 0x100b0 0x2c0 0x6a8 0x814 0x1 0x1 0x1b0b0 0x2ac 0x694 0x818 0x1 0x1 0x1b0b0 0x2b0 0x698 0x81c 0x1 0x1 0x1b0b0 0x2b4 0x69c 0x820 0x1 0x1 0x1b0b0 0x2b8 0x6a0 0x824 0x1 0x1 0x1b0b0 0x2bc 0x6a4 0x828 0x1 0x1 0x1b0b0>;
  826. linux,phandle = <0x1c>;
  827. phandle = <0x1c>;
  828. };
  829.  
  830. enetgrp-2 {
  831. fsl,pins = <0x248 0x630 0x810 0x1 0x1 0x1b0b0 0x24c 0x634 0x0 0x4 0x0 0x1b0b0 0x2d8 0x6c0 0x0 0x1 0x0 0x1b0b0 0x2c4 0x6ac 0x0 0x1 0x0 0x1b0b0 0x2c8 0x6b0 0x0 0x1 0x0 0x1b0b0 0x2cc 0x6b4 0x0 0x1 0x0 0x1b0b0 0x2d0 0x6b8 0x0 0x1 0x0 0x1b0b0 0x2d4 0x6bc 0x0 0x1 0x0 0x1b0b0 0x1f0 0x5c0 0x0 0x1 0x0 0x1b0b0 0x2c0 0x6a8 0x814 0x1 0x1 0x1b0b0 0x2ac 0x694 0x818 0x1 0x1 0x1b0b0 0x2b0 0x698 0x81c 0x1 0x1 0x1b0b0 0x2b4 0x69c 0x820 0x1 0x1 0x1b0b0 0x2b8 0x6a0 0x824 0x1 0x1 0x1b0b0 0x2bc 0x6a4 0x828 0x1 0x1 0x1b0b0 0x214 0x5e4 0x80c 0x2 0x0 0x4001b0a8>;
  832. };
  833.  
  834. enetgrp-3 {
  835. fsl,pins = <0x1ec 0x5bc 0x810 0x1 0x0 0x1b0b0 0x1e8 0x5b8 0x0 0x1 0x0 0x1b0b0 0x2d8 0x6c0 0x0 0x1 0x0 0x1b0b0 0x2c4 0x6ac 0x0 0x1 0x0 0x1b0b0 0x2c8 0x6b0 0x0 0x1 0x0 0x1b0b0 0x2cc 0x6b4 0x0 0x1 0x0 0x1b0b0 0x2d0 0x6b8 0x0 0x1 0x0 0x1b0b0 0x2d4 0x6bc 0x0 0x1 0x0 0x1b0b0 0x1f0 0x5c0 0x0 0x1 0x0 0x1b0b0 0x2c0 0x6a8 0x814 0x1 0x1 0x1b0b0 0x2ac 0x694 0x818 0x1 0x1 0x1b0b0 0x2b0 0x698 0x81c 0x1 0x1 0x1b0b0 0x2b4 0x69c 0x820 0x1 0x1 0x1b0b0 0x2b8 0x6a0 0x824 0x1 0x1 0x1b0b0 0x2bc 0x6a4 0x828 0x1 0x1 0x1b0b0 0x200 0x5d0 0x0 0x1 0x0 0x1b0b0>;
  836. };
  837. };
  838.  
  839. esai {
  840.  
  841. esaigrp-1 {
  842. fsl,pins = <0x1f8 0x5c8 0x838 0x2 0x0 0x1b030 0x1e4 0x5b4 0x840 0x2 0x0 0x1b030 0x1fc 0x5cc 0x830 0x2 0x0 0x1b030 0x200 0x5d0 0x850 0x2 0x0 0x1b030 0x208 0x5d8 0x84c 0x2 0x0 0x1b030 0x204 0x5d4 0x854 0x2 0x0 0x1b030 0x1e8 0x5b8 0x858 0x2 0x0 0x1b030 0x27c 0x664 0x844 0x2 0x1 0x1b030 0x280 0x668 0x848 0x2 0x1 0x1b030>;
  843. };
  844.  
  845. esaigrp-2 {
  846. fsl,pins = <0x1e4 0x5b4 0x840 0x2 0x0 0x1b030 0x1fc 0x5cc 0x830 0x2 0x0 0x1b030 0x200 0x5d0 0x850 0x2 0x0 0x1b030 0x230 0x600 0x84c 0x0 0x1 0x1b030 0x204 0x5d4 0x854 0x2 0x0 0x1b030 0x1e8 0x5b8 0x858 0x2 0x0 0x1b030 0x218 0x5e8 0x844 0x0 0x0 0x1b030 0x280 0x668 0x848 0x2 0x1 0x1b030 0x1ec 0x5bc 0x83c 0x2 0x0 0x1b030 0x240 0x610 0x82c 0x0 0x1 0x1b030>;
  847. };
  848. };
  849.  
  850. flexcan1 {
  851.  
  852. flexcan1grp-1 {
  853. fsl,pins = <0x260 0x648 0x7c8 0x2 0x1 0x80000000 0x24c 0x634 0x0 0x2 0x0 0x80000000>;
  854. linux,phandle = <0x10>;
  855. phandle = <0x10>;
  856. };
  857.  
  858. flexcan1grp-2 {
  859. fsl,pins = <0x238 0x608 0x0 0x3 0x0 0x80000000 0x260 0x648 0x7c8 0x2 0x1 0x80000000>;
  860. };
  861. };
  862.  
  863. flexcan2 {
  864.  
  865. flexcan2grp-1 {
  866. fsl,pins = <0x254 0x63c 0x0 0x0 0x0 0x80000000 0x268 0x650 0x7cc 0x0 0x0 0x80000000>;
  867. };
  868. };
  869.  
  870. gpmi-nand {
  871.  
  872. gpmi-nand-1 {
  873. fsl,pins = <0x270 0x658 0x0 0x0 0x0 0xb0b1 0x26c 0x654 0x0 0x0 0x0 0xb0b1 0x2a8 0x690 0x0 0x0 0x0 0xb0b1 0x2a4 0x68c 0x0 0x0 0x0 0xb000 0x274 0x65c 0x0 0x0 0x0 0xb0b1 0x278 0x660 0x0 0x0 0x0 0xb0b1 0x33c 0x724 0x0 0x1 0x0 0xb0b1 0x338 0x720 0x0 0x1 0x0 0xb0b1 0x284 0x66c 0x0 0x0 0x0 0xb0b1 0x288 0x670 0x0 0x0 0x0 0xb0b1 0x28c 0x674 0x0 0x0 0x0 0xb0b1 0x290 0x678 0x0 0x0 0x0 0xb0b1 0x294 0x67c 0x0 0x0 0x0 0xb0b1 0x298 0x680 0x0 0x0 0x0 0xb0b1 0x29c 0x684 0x0 0x0 0x0 0xb0b1 0x2a0 0x688 0x0 0x0 0x0 0xb0b1 0x340 0x728 0x0 0x2 0x0 0xb1>;
  874. linux,phandle = <0x4>;
  875. phandle = <0x4>;
  876. };
  877. };
  878.  
  879. hdmi_hdcp {
  880.  
  881. hdmihdcpgrp-1 {
  882. fsl,pins = <0x250 0x638 0x860 0x2 0x1 0x4001b8b1 0x264 0x64c 0x864 0x2 0x1 0x4001b8b1>;
  883. };
  884.  
  885. hdmihdcpgrp-2 {
  886. fsl,pins = <0x1cc 0x59c 0x860 0x4 0x0 0x4001b8b1 0x144 0x514 0x864 0x4 0x0 0x4001b8b1>;
  887. };
  888.  
  889. hdmihdcpgrp-3 {
  890. fsl,pins = <0x1cc 0x59c 0x860 0x4 0x0 0x4001b8b1 0x264 0x64c 0x864 0x2 0x1 0x4001b8b1>;
  891. };
  892. };
  893.  
  894. hdmi_cec {
  895.  
  896. hdmicecgrp-1 {
  897. fsl,pins = <0x134 0x504 0x85c 0x6 0x0 0x1f8b0>;
  898. };
  899.  
  900. hdmicecgrp-2 {
  901. fsl,pins = <0x260 0x648 0x85c 0x6 0x1 0x1f8b0>;
  902. };
  903. };
  904.  
  905. i2c1 {
  906.  
  907. i2c1grp-1 {
  908. fsl,pins = <0x158 0x528 0x868 0x6 0x1 0x4001b8b1 0x174 0x544 0x86c 0x1 0x1 0x4001b8b1>;
  909. };
  910.  
  911. i2c1grp-2 {
  912. fsl,pins = <0x84 0x398 0x86c 0x4 0x0 0x4001b8b1 0x88 0x39c 0x868 0x4 0x0 0x4001b8b1>;
  913. linux,phandle = <0x22>;
  914. phandle = <0x22>;
  915. };
  916. };
  917.  
  918. i2c2 {
  919.  
  920. i2c2grp-1 {
  921. fsl,pins = <0x1cc 0x59c 0x870 0x6 0x0 0x4001b8b1 0x144 0x514 0x874 0x6 0x0 0x4001b8b1>;
  922. };
  923.  
  924. i2c2grp-2 {
  925. fsl,pins = <0x250 0x638 0x870 0x4 0x1 0x4001b8b1 0x264 0x64c 0x874 0x4 0x1 0x4001b8b1>;
  926. linux,phandle = <0x27>;
  927. phandle = <0x27>;
  928. };
  929.  
  930. i2c2grp-3 {
  931. fsl,pins = <0x1cc 0x59c 0x870 0x6 0x0 0x4001b8b1 0x264 0x64c 0x874 0x4 0x1 0x4001b8b1>;
  932. };
  933. };
  934.  
  935. i2c3 {
  936.  
  937. i2c3grp-1 {
  938. fsl,pins = <0x148 0x518 0x878 0x6 0x0 0x4001b8b1 0x14c 0x51c 0x87c 0x6 0x0 0x4001b8b1>;
  939. };
  940.  
  941. i2c3grp-2 {
  942. fsl,pins = <0x228 0x5f8 0x878 0x2 0x1 0x4001b8b1 0x234 0x604 0x87c 0x2 0x2 0x4001b8b1>;
  943. };
  944.  
  945. i2c3grp-3 {
  946. fsl,pins = <0x230 0x600 0x878 0x6 0x2 0x4001b8b1 0x214 0x5e4 0x87c 0x6 0x1 0x4001b8b1>;
  947. };
  948.  
  949. i2c3grp-4 {
  950. fsl,pins = <0x228 0x5f8 0x878 0x2 0x1 0x4001b8b1 0x14c 0x51c 0x87c 0x6 0x0 0x4001b8b1>;
  951. };
  952. };
  953.  
  954. ipu1 {
  955.  
  956. ipu1grp-1 {
  957. fsl,pins = <0x9c 0x3b0 0x0 0x0 0x0 0x10 0xa0 0x3b4 0x0 0x0 0x0 0x10 0xa4 0x3b8 0x0 0x0 0x0 0x10 0xa8 0x3bc 0x0 0x0 0x0 0x10 0xac 0x3c0 0x0 0x0 0x0 0x80000000 0xb0 0x3c4 0x0 0x0 0x0 0x10 0xb4 0x3c8 0x0 0x0 0x0 0x10 0xe0 0x3f4 0x0 0x0 0x0 0x10 0xf4 0x408 0x0 0x0 0x0 0x10 0xf8 0x40c 0x0 0x0 0x0 0x10 0xfc 0x410 0x0 0x0 0x0 0x10 0x100 0x414 0x0 0x0 0x0 0x10 0x104 0x418 0x0 0x0 0x0 0x10 0x108 0x41c 0x0 0x0 0x0 0x10 0x10c 0x420 0x0 0x0 0x0 0x10 0xb8 0x3cc 0x0 0x0 0x0 0x10 0xbc 0x3d0 0x0 0x0 0x0 0x10 0xc0 0x3d4 0x0 0x0 0x0 0x10 0xc4 0x3d8 0x0 0x0 0x0 0x10 0xc8 0x3dc 0x0 0x0 0x0 0x10 0xcc 0x3e0 0x0 0x0 0x0 0x10 0xd0 0x3e4 0x0 0x0 0x0 0x10 0xd4 0x3e8 0x0 0x0 0x0 0x10 0xd8 0x3ec 0x0 0x0 0x0 0x10 0xdc 0x3f0 0x0 0x0 0x0 0x10 0xe4 0x3f8 0x0 0x0 0x0 0x10 0xe8 0x3fc 0x0 0x0 0x0 0x10 0xec 0x400 0x0 0x0 0x0 0x10 0xf0 0x404 0x0 0x0 0x0 0x10>;
  958. };
  959.  
  960. ipu1grp-2 {
  961. fsl,pins = <0x54 0x368 0x0 0x0 0x0 0x80000000 0x58 0x36c 0x0 0x0 0x0 0x80000000 0x5c 0x370 0x0 0x0 0x0 0x80000000 0x60 0x374 0x0 0x0 0x0 0x80000000 0x64 0x378 0x0 0x0 0x0 0x80000000 0x68 0x37c 0x0 0x0 0x0 0x80000000 0x6c 0x380 0x0 0x0 0x0 0x80000000 0x70 0x384 0x0 0x0 0x0 0x80000000 0x8c 0x3a0 0x0 0x0 0x0 0x80000000 0x94 0x3a8 0x0 0x0 0x0 0x80000000 0x90 0x3a4 0x0 0x0 0x0 0x80000000 0x98 0x3ac 0x0 0x0 0x0 0x80000000>;
  962. linux,phandle = <0x23>;
  963. phandle = <0x23>;
  964. };
  965.  
  966. ipu1grp-3 {
  967. fsl,pins = <0x74 0x388 0x0 0x0 0x0 0x80000000 0x78 0x38c 0x0 0x0 0x0 0x80000000 0x7c 0x390 0x0 0x0 0x0 0x80000000 0x80 0x394 0x0 0x0 0x0 0x80000000 0x84 0x398 0x0 0x0 0x0 0x80000000 0x88 0x39c 0x0 0x0 0x0 0x80000000 0x4c 0x360 0x0 0x0 0x0 0x80000000 0x50 0x364 0x0 0x0 0x0 0x80000000 0x54 0x368 0x0 0x0 0x0 0x80000000 0x58 0x36c 0x0 0x0 0x0 0x80000000 0x5c 0x370 0x0 0x0 0x0 0x80000000 0x60 0x374 0x0 0x0 0x0 0x80000000 0x64 0x378 0x0 0x0 0x0 0x80000000 0x68 0x37c 0x0 0x0 0x0 0x80000000 0x6c 0x380 0x0 0x0 0x0 0x80000000 0x70 0x384 0x0 0x0 0x0 0x80000000 0x94 0x3a8 0x0 0x0 0x0 0x80000000 0x90 0x3a4 0x0 0x0 0x0 0x80000000 0x98 0x3ac 0x0 0x0 0x0 0x80000000>;
  968. };
  969.  
  970. ipu1grp {
  971. fsl,pins = <0x9c 0x3b0 0x0 0x0 0x0 0x10 0xa0 0x3b4 0x0 0x0 0x0 0x10 0xa4 0x3b8 0x0 0x0 0x0 0x10 0xa8 0x3bc 0x0 0x0 0x0 0x10 0xb0 0x3c4 0x0 0x0 0x0 0x10 0xb4 0x3c8 0x0 0x0 0x0 0x10 0xe0 0x3f4 0x0 0x0 0x0 0x10 0xf4 0x408 0x0 0x0 0x0 0x10 0xf8 0x40c 0x0 0x0 0x0 0x10 0xfc 0x410 0x0 0x0 0x0 0x10 0x100 0x414 0x0 0x0 0x0 0x10 0x104 0x418 0x0 0x0 0x0 0x10 0x108 0x41c 0x0 0x0 0x0 0x10 0x10c 0x420 0x0 0x0 0x0 0x10 0xb8 0x3cc 0x0 0x0 0x0 0x10 0xbc 0x3d0 0x0 0x0 0x0 0x10 0xc0 0x3d4 0x0 0x0 0x0 0x10 0xc4 0x3d8 0x0 0x0 0x0 0x10 0xc8 0x3dc 0x0 0x0 0x0 0x10 0xcc 0x3e0 0x0 0x0 0x0 0x10 0xd0 0x3e4 0x0 0x0 0x0 0x10 0xd4 0x3e8 0x0 0x0 0x0 0x10 0xd8 0x3ec 0x0 0x0 0x0 0x10 0xdc 0x3f0 0x0 0x0 0x0 0x10 0xe4 0x3f8 0x0 0x0 0x0 0x10 0xe8 0x3fc 0x0 0x0 0x0 0x10 0xec 0x400 0x0 0x0 0x0 0x10 0xf0 0x404 0x0 0x0 0x0 0x10>;
  972. };
  973. };
  974.  
  975. mlb {
  976.  
  977. mlbgrp-1 {
  978. fsl,pins = <0x228 0x5f8 0x8dc 0x7 0x1 0x71 0x234 0x604 0x8e4 0x7 0x1 0x71 0x224 0x5f4 0x8e0 0x7 0x1 0x71>;
  979. };
  980.  
  981. mlbgrp-2 {
  982. fsl,pins = <0x208 0x5d8 0x8dc 0x0 0x0 0x80000000 0x234 0x604 0x8e4 0x7 0x1 0x80000000 0x224 0x5f4 0x8e0 0x7 0x1 0x80000000>;
  983. };
  984. };
  985.  
  986. pwm1 {
  987.  
  988. pwm1grp-1 {
  989. fsl,pins = <0x2f0 0x6d8 0x0 0x3 0x0 0x1b0b1>;
  990. };
  991. };
  992.  
  993. pwm3 {
  994.  
  995. pwm3grp-1 {
  996. fsl,pins = <0x344 0x72c 0x0 0x2 0x0 0x1b0b1>;
  997. };
  998. };
  999.  
  1000. spdif {
  1001.  
  1002. spdifgrp-1 {
  1003. fsl,pins = <0x250 0x638 0x8f0 0x6 0x3 0x1b0b0>;
  1004. };
  1005.  
  1006. spdifgrp-2 {
  1007. fsl,pins = <0x214 0x5e4 0x8f0 0x4 0x2 0x1b0b0 0x218 0x5e8 0x0 0x4 0x0 0x1b0b0>;
  1008. };
  1009. };
  1010.  
  1011. uart1 {
  1012.  
  1013. uart1grp-1 {
  1014. fsl,pins = <0x4c 0x360 0x0 0x3 0x0 0x1b0b1 0x50 0x364 0x8fc 0x3 0x1 0x1b0b1>;
  1015. };
  1016.  
  1017. uart1grp {
  1018. fsl,pins = <0x4c 0x360 0x0 0x3 0x0 0x1b0b1 0x50 0x364 0x8fc 0x3 0x1 0x1b0b1 0x150 0x520 0x0 0x4 0x0 0x1b0b1 0x154 0x524 0x8f8 0x4 0x1 0x1b0b1>;
  1019. linux,phandle = <0xa>;
  1020. phandle = <0xa>;
  1021. };
  1022. };
  1023.  
  1024. uart2 {
  1025.  
  1026. uart2grp-1 {
  1027. fsl,pins = <0x16c 0x53c 0x0 0x4 0x0 0x1b0b1 0x170 0x540 0x904 0x4 0x1 0x1b0b1>;
  1028. linux,phandle = <0x2a>;
  1029. phandle = <0x2a>;
  1030. };
  1031.  
  1032. uart2grp-2 {
  1033. fsl,pins = <0x16c 0x53c 0x904 0x4 0x0 0x1b0b1 0x170 0x540 0x0 0x4 0x0 0x1b0b1 0x174 0x544 0x900 0x4 0x0 0x1b0b1 0x178 0x548 0x0 0x4 0x0 0x1b0b1>;
  1034. };
  1035. };
  1036.  
  1037. uart3 {
  1038.  
  1039. uart3grp-1 {
  1040. fsl,pins = <0x338 0x720 0x90c 0x2 0x2 0x1b0b1 0x33c 0x724 0x0 0x2 0x0 0x1b0b1 0x17c 0x54c 0x0 0x4 0x0 0x1b0b1 0x1d0 0x5a0 0x908 0x2 0x3 0x1b0b1>;
  1041. };
  1042.  
  1043. uart3grp {
  1044. fsl,pins = <0x160 0x530 0x0 0x2 0x0 0x1b0b1 0x180 0x550 0x908 0x4 0x2 0x1b0b1 0x168 0x538 0x90c 0x2 0x1 0x1b0b1 0x164 0x534 0x0 0x2 0x0 0x1b0b1>;
  1045. linux,phandle = <0x2b>;
  1046. phandle = <0x2b>;
  1047. };
  1048. };
  1049.  
  1050. uart4 {
  1051.  
  1052. uart4grp-1 {
  1053. fsl,pins = <0x244 0x62c 0x0 0x4 0x0 0x1b0b1 0x258 0x640 0x914 0x4 0x3 0x1b0b1>;
  1054. };
  1055. };
  1056.  
  1057. usbotg {
  1058.  
  1059. usbotggrp-1 {
  1060. fsl,pins = <0x210 0x5e0 0x790 0x3 0x1 0x17059>;
  1061. };
  1062.  
  1063. usbotggrp-2 {
  1064. fsl,pins = <0x1f4 0x5c4 0x790 0x0 0x0 0x17059>;
  1065. };
  1066.  
  1067. usbotggrp {
  1068. fsl,pins = <0x210 0x5e0 0x790 0x3 0x1 0x17059 0x254 0x63c 0x920 0x2 0x1 0x1b0b0>;
  1069. linux,phandle = <0x17>;
  1070. phandle = <0x17>;
  1071. };
  1072. };
  1073.  
  1074. usbh2 {
  1075.  
  1076. usbh2grp-1 {
  1077. fsl,pins = <0x2d8 0x6c0 0x0 0x0 0x0 0x40013030 0x2d4 0x6bc 0x0 0x0 0x0 0x40013030>;
  1078. };
  1079.  
  1080. usbh2grp-2 {
  1081. fsl,pins = <0x2d4 0x6bc 0x0 0x0 0x0 0x40017030>;
  1082. };
  1083. };
  1084.  
  1085. usbh3 {
  1086.  
  1087. usbh3grp-1 {
  1088. fsl,pins = <0x2bc 0x6a4 0x0 0x0 0x0 0x40013030 0x2c0 0x6a8 0x0 0x0 0x0 0x40013030>;
  1089. };
  1090.  
  1091. usbh3grp-2 {
  1092. fsl,pins = <0x2c0 0x6a8 0x0 0x0 0x0 0x40017030>;
  1093. };
  1094. };
  1095.  
  1096. usdhc1 {
  1097.  
  1098. usdhc1grp-1 {
  1099. fsl,pins = <0x2e0 0x6c8 0x0 0x0 0x0 0x17071 0x2dc 0x6c4 0x928 0x0 0x1 0x10071 0x2e4 0x6cc 0x0 0x0 0x0 0x17071 0x2e8 0x6d0 0x0 0x0 0x0 0x17071 0x2ec 0x6d4 0x0 0x0 0x0 0x17071 0x2f0 0x6d8 0x0 0x0 0x0 0x17071>;
  1100. linux,phandle = <0x1d>;
  1101. phandle = <0x1d>;
  1102. };
  1103. };
  1104.  
  1105. usdhc2 {
  1106.  
  1107. usdhc2grp-1 {
  1108. fsl,pins = <0x2f8 0x6e0 0x0 0x0 0x0 0x17059 0x2f4 0x6dc 0x930 0x0 0x1 0x10059 0x2fc 0x6e4 0x0 0x0 0x0 0x17059 0x300 0x6e8 0x0 0x0 0x0 0x17059 0x304 0x6ec 0x0 0x0 0x0 0x17059 0x308 0x6f0 0x0 0x0 0x0 0x17059 0x294 0x67c 0x0 0x1 0x0 0x17059 0x298 0x680 0x0 0x1 0x0 0x17059 0x29c 0x684 0x0 0x1 0x0 0x17059 0x2a0 0x688 0x0 0x1 0x0 0x17059>;
  1109. };
  1110.  
  1111. usdhc2grp-2 {
  1112. fsl,pins = <0x2f8 0x6e0 0x0 0x0 0x0 0x17059 0x2f4 0x6dc 0x930 0x0 0x1 0x10059 0x2fc 0x6e4 0x0 0x0 0x0 0x17059 0x300 0x6e8 0x0 0x0 0x0 0x17059 0x304 0x6ec 0x0 0x0 0x0 0x17059 0x308 0x6f0 0x0 0x0 0x0 0x17059>;
  1113. linux,phandle = <0x1e>;
  1114. phandle = <0x1e>;
  1115. };
  1116. };
  1117.  
  1118. usdhc3 {
  1119.  
  1120. usdhc3grp-1 {
  1121. fsl,pins = <0x310 0x6f8 0x0 0x0 0x0 0x17059 0x30c 0x6f4 0x934 0x0 0x1 0x10059 0x314 0x6fc 0x0 0x0 0x0 0x17059 0x318 0x700 0x0 0x0 0x0 0x17059 0x31c 0x704 0x0 0x0 0x0 0x17059 0x320 0x708 0x0 0x0 0x0 0x17059 0x324 0x70c 0x0 0x0 0x0 0x17059 0x328 0x710 0x0 0x0 0x0 0x17059 0x32c 0x714 0x0 0x0 0x0 0x17059 0x330 0x718 0x0 0x0 0x0 0x17059>;
  1122. };
  1123.  
  1124. usdhc3grp-1-100mhz {
  1125. fsl,pins = <0x310 0x6f8 0x0 0x0 0x0 0x17109 0x30c 0x6f4 0x934 0x0 0x1 0x10109 0x314 0x6fc 0x0 0x0 0x0 0x17109 0x318 0x700 0x0 0x0 0x0 0x17109 0x31c 0x704 0x0 0x0 0x0 0x17109 0x320 0x708 0x0 0x0 0x0 0x17109 0x324 0x70c 0x0 0x0 0x0 0x17109 0x328 0x710 0x0 0x0 0x0 0x17109 0x32c 0x714 0x0 0x0 0x0 0x17109 0x330 0x718 0x0 0x0 0x0 0x17109 0x334 0x71c 0x0 0x5 0x0 0x4001b8b1>;
  1126. linux,phandle = <0x20>;
  1127. phandle = <0x20>;
  1128. };
  1129.  
  1130. usdhc3grp-1-200mhz {
  1131. fsl,pins = <0x310 0x6f8 0x0 0x0 0x0 0x170f9 0x30c 0x6f4 0x934 0x0 0x1 0x100f9 0x314 0x6fc 0x0 0x0 0x0 0x170f9 0x318 0x700 0x0 0x0 0x0 0x170f9 0x31c 0x704 0x0 0x0 0x0 0x170f9 0x320 0x708 0x0 0x0 0x0 0x170f9 0x324 0x70c 0x0 0x0 0x0 0x170f9 0x328 0x710 0x0 0x0 0x0 0x170f9 0x32c 0x714 0x0 0x0 0x0 0x170f9 0x330 0x718 0x0 0x0 0x0 0x170f9>;
  1132. };
  1133.  
  1134. usdhc3grp-2 {
  1135. fsl,pins = <0x310 0x6f8 0x0 0x0 0x0 0x17059 0x30c 0x6f4 0x934 0x0 0x1 0x10059 0x314 0x6fc 0x0 0x0 0x0 0x17059 0x318 0x700 0x0 0x0 0x0 0x17059 0x31c 0x704 0x0 0x0 0x0 0x17059 0x320 0x708 0x0 0x0 0x0 0x17059>;
  1136. };
  1137. };
  1138.  
  1139. usdhc4 {
  1140.  
  1141. usdhc4grp-1 {
  1142. fsl,pins = <0x33c 0x724 0x0 0x0 0x0 0x17059 0x338 0x720 0x938 0x0 0x1 0x10059 0x340 0x728 0x0 0x1 0x0 0x17059 0x344 0x72c 0x0 0x1 0x0 0x17059 0x348 0x730 0x0 0x1 0x0 0x17059 0x34c 0x734 0x0 0x1 0x0 0x17059 0x350 0x738 0x0 0x1 0x0 0x17059 0x354 0x73c 0x0 0x1 0x0 0x17059 0x358 0x740 0x0 0x1 0x0 0x17059 0x35c 0x744 0x0 0x1 0x0 0x17059>;
  1143. };
  1144.  
  1145. usdhc4grp-2 {
  1146. fsl,pins = <0x33c 0x724 0x0 0x0 0x0 0x17059 0x338 0x720 0x938 0x0 0x1 0x10059 0x340 0x728 0x0 0x1 0x0 0x17059 0x344 0x72c 0x0 0x1 0x0 0x17059 0x348 0x730 0x0 0x1 0x0 0x17059 0x34c 0x734 0x0 0x1 0x0 0x17059>;
  1147. };
  1148. };
  1149.  
  1150. weim {
  1151.  
  1152. weim_cs0grp-1 {
  1153. fsl,pins = <0x13c 0x50c 0x0 0x0 0x0 0xb0b1>;
  1154. };
  1155.  
  1156. weim_norgrp-1 {
  1157. fsl,pins = <0x1d8 0x5a8 0x0 0x0 0x0 0xb0b1 0x1dc 0x5ac 0x0 0x0 0x0 0xb0b1 0x1e0 0x5b0 0x0 0x0 0x0 0xb060 0x144 0x514 0x0 0x0 0x0 0x1b0b0 0x148 0x518 0x0 0x0 0x0 0x1b0b0 0x14c 0x51c 0x0 0x0 0x0 0x1b0b0 0x150 0x520 0x0 0x0 0x0 0x1b0b0 0x154 0x524 0x0 0x0 0x0 0x1b0b0 0x158 0x528 0x0 0x0 0x0 0x1b0b0 0x15c 0x52c 0x0 0x0 0x0 0x1b0b0 0x160 0x530 0x0 0x0 0x0 0x1b0b0 0x164 0x534 0x0 0x0 0x0 0x1b0b0 0x168 0x538 0x0 0x0 0x0 0x1b0b0 0x16c 0x53c 0x0 0x0 0x0 0x1b0b0 0x170 0x540 0x0 0x0 0x0 0x1b0b0 0x174 0x544 0x0 0x0 0x0 0x1b0b0 0x178 0x548 0x0 0x0 0x0 0x1b0b0 0x17c 0x54c 0x0 0x0 0x0 0x1b0b0 0x180 0x550 0x0 0x0 0x0 0x1b0b0 0x12c 0x4fc 0x0 0x0 0x0 0xb0b1 0x128 0x4f8 0x0 0x0 0x0 0xb0b1 0x124 0x4f4 0x0 0x0 0x0 0xb0b1 0x120 0x4f0 0x0 0x0 0x0 0xb0b1 0x11c 0x4ec 0x0 0x0 0x0 0xb0b1 0x118 0x4e8 0x0 0x0 0x0 0xb0b1 0x114 0x4e4 0x0 0x0 0x0 0xb0b1 0x110 0x4e0 0x0 0x0 0x0 0xb0b1 0x1a0 0x570 0x0 0x0 0x0 0xb0b1 0x19c 0x56c 0x0 0x0 0x0 0xb0b1 0x198 0x568 0x0 0x0 0x0 0xb0b1 0x194 0x564 0x0 0x0 0x0 0xb0b1 0x190 0x560 0x0 0x0 0x0 0xb0b1 0x18c 0x55c 0x0 0x0 0x0 0xb0b1 0x1c0 0x590 0x0 0x0 0x0 0xb0b1 0x1bc 0x58c 0x0 0x0 0x0 0xb0b1 0x1b8 0x588 0x0 0x0 0x0 0xb0b1 0x1b4 0x584 0x0 0x0 0x0 0xb0b1 0x1b0 0x580 0x0 0x0 0x0 0xb0b1 0x1ac 0x57c 0x0 0x0 0x0 0xb0b1 0x1a8 0x578 0x0 0x0 0x0 0xb0b1 0x1a4 0x574 0x0 0x0 0x0 0xb0b1 0x188 0x558 0x0 0x0 0x0 0xb0b1 0x184 0x554 0x0 0x0 0x0 0xb0b1>;
  1158. };
  1159. };
  1160.  
  1161. epdc {
  1162.  
  1163. epdcgrp-0 {
  1164. fsl,pins = <0x110 0x4e0 0x0 0x8 0x0 0x80000000 0x18c 0x55c 0x0 0x8 0x0 0x80000000 0x194 0x564 0x0 0x8 0x0 0x80000000 0x190 0x560 0x0 0x8 0x0 0x80000000 0x1d4 0x5a4 0x0 0x8 0x0 0x80000000 0x1cc 0x59c 0x0 0x8 0x0 0x80000000 0x13c 0x50c 0x0 0x8 0x0 0x80000000 0x1dc 0x5ac 0x0 0x8 0x0 0x80000000 0x124 0x4f4 0x0 0x8 0x0 0x80000000 0x128 0x4f8 0x0 0x8 0x0 0x80000000 0x12c 0x4fc 0x0 0x8 0x0 0x80000000 0x130 0x500 0x0 0x8 0x0 0x80000000 0x180 0x550 0x0 0x8 0x0 0x80000000 0x170 0x540 0x0 0x8 0x0 0x80000000 0x188 0x558 0x0 0x8 0x0 0x80000000 0x1c8 0x598 0x0 0x8 0x0 0x80000000 0x1a4 0x574 0x0 0x8 0x0 0x80000000 0x1ac 0x57c 0x0 0x8 0x0 0x80000000 0x1b0 0x580 0x0 0x8 0x0 0x80000000 0x1b4 0x584 0x0 0x8 0x0 0x80000000>;
  1165. };
  1166. };
  1167.  
  1168. led {
  1169.  
  1170. led1grp-1 {
  1171. fsl,pins = <0x1f4 0x5c4 0x0 0x5 0x0 0x80000000 0x1cc 0x59c 0x0 0x5 0x0 0x80000000 0x1e4 0x5b4 0x0 0x5 0x0 0x80000000>;
  1172. linux,phandle = <0x30>;
  1173. phandle = <0x30>;
  1174. };
  1175. };
  1176.  
  1177. pwm {
  1178.  
  1179. pwm1grp-2 {
  1180. fsl,pins = <0x240 0x610 0x0 0x4 0x0 0x1b0b1>;
  1181. linux,phandle = <0xe>;
  1182. phandle = <0xe>;
  1183. };
  1184.  
  1185. pwm4grp-1 {
  1186. fsl,pins = <0x348 0x730 0x0 0x2 0x0 0x1b0b1>;
  1187. };
  1188. };
  1189.  
  1190. ecspi4 {
  1191.  
  1192. ecspi4grp-1 {
  1193. fsl,pins = <0x15c 0x52c 0x0 0x1 0x0 0x100b1 0x174 0x544 0x0 0x2 0x0 0x100b1 0x158 0x528 0x0 0x1 0x0 0x100b1>;
  1194. linux,phandle = <0x9>;
  1195. phandle = <0x9>;
  1196. };
  1197. };
  1198.  
  1199. pmic {
  1200.  
  1201. pinctrl_pmicirqgrp-1 {
  1202. fsl,pins = <0x218 0x5e8 0x0 0x5 0x0 0x1f0b0>;
  1203. linux,phandle = <0x28>;
  1204. phandle = <0x28>;
  1205. };
  1206. };
  1207.  
  1208. hog {
  1209.  
  1210. hoggrp-1 {
  1211. fsl,pins = <0x12c 0x4fc 0x0 0x5 0x0 0x30b1 0x144 0x514 0x0 0x5 0x0 0x30b1 0x114 0x4e4 0x0 0x5 0x0 0x30b1 0x110 0x4e0 0x0 0x5 0x0 0x30b1 0x118 0x4e8 0x0 0x5 0x0 0x30b1 0x11c 0x4ec 0x0 0x5 0x0 0x30b1 0x124 0x4f4 0x0 0x5 0x0 0x30b1 0x120 0x4f0 0x0 0x5 0x0 0x30b1 0x124 0x4f4 0x0 0x5 0x0 0x30b1 0x128 0x4f8 0x0 0x5 0x0 0x30b1 0x130 0x500 0x0 0x5 0x0 0x30b1 0x1d4 0x5a4 0x0 0x5 0x0 0x30b1 0x1d0 0x5a0 0x0 0x5 0x0 0x30b1 0x134 0x504 0x0 0x5 0x0 0x30b1 0x228 0x5f8 0x0 0x5 0x0 0x30b1 0xac 0x3c0 0x0 0x5 0x0 0x30b1 0x238 0x608 0x0 0x5 0x0 0x30b1 0x90 0x3a4 0x0 0x3 0x0 0x130b0>;
  1212. linux,phandle = <0x13>;
  1213. phandle = <0x13>;
  1214. };
  1215. };
  1216.  
  1217. i2c4 {
  1218.  
  1219. i2c4grp-1 {
  1220. fsl,pins = <0x238 0x608 0x880 0x8 0x1 0x4001b8b1 0x23c 0x60c 0x884 0x8 0x1 0x4001b8b1>;
  1221. };
  1222. };
  1223. };
  1224.  
  1225. ldb@020e0008 {
  1226. compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
  1227. reg = <0x20e0000 0x4000>;
  1228. clocks = <0x2 0x87 0x2 0x88 0x2 0x27 0x2 0x28 0x2 0x29 0x2 0x2a 0x2 0xb8 0x2 0xb9 0x2 0xcd 0x2 0xce 0x2 0xcf 0x2 0xd0>;
  1229. clock-names = "ldb_di0", "ldb_di1", "ipu1_di0_sel", "ipu1_di1_sel", "ipu2_di0_sel", "ipu2_di1_sel", "di0_div_3_5", "di1_div_3_5", "di0_div_7", "di1_div_7", "di0_div_sel", "di1_div_sel";
  1230. status = "okay";
  1231. ipu_id = <0x0>;
  1232. disp_id = <0x1>;
  1233. ext_ref = <0x1>;
  1234. mode = "sin0";
  1235. sec_ipu_id = <0x1>;
  1236. sec_disp_id = <0x1>;
  1237. };
  1238.  
  1239. dcic@020e4000 {
  1240. reg = <0x20e4000 0x4000>;
  1241. interrupts = <0x0 0x7c 0x4>;
  1242. };
  1243.  
  1244. dcic@020e8000 {
  1245. reg = <0x20e8000 0x4000>;
  1246. interrupts = <0x0 0x7d 0x4>;
  1247. };
  1248.  
  1249. sdma@020ec000 {
  1250. compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
  1251. reg = <0x20ec000 0x4000>;
  1252. interrupts = <0x0 0x2 0x4>;
  1253. clocks = <0x2 0x9b 0x2 0x9b>;
  1254. clock-names = "ipg", "ahb";
  1255. #dma-cells = <0x3>;
  1256. fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
  1257. linux,phandle = <0x6>;
  1258. phandle = <0x6>;
  1259. };
  1260.  
  1261. pxp@020f0000 {
  1262. compatible = "fsl,imx6dl-pxp-dma";
  1263. reg = <0x20f0000 0x4000>;
  1264. interrupts = <0x0 0x62 0x4>;
  1265. clocks = <0x2 0x85>;
  1266. clock-names = "pxp-axi";
  1267. status = "disabled";
  1268. };
  1269.  
  1270. epdc@020f4000 {
  1271. compatible = "fsl,imx6dl-epdc";
  1272. reg = <0x20f4000 0x4000>;
  1273. interrupts = <0x0 0x61 0x4>;
  1274. clocks = <0x2 0x85 0x2 0x89>;
  1275. clock-names = "epdc_axi", "epdc_pix";
  1276. };
  1277.  
  1278. lcdif@020f8000 {
  1279. reg = <0x20f8000 0x4000>;
  1280. interrupts = <0x0 0x27 0x4>;
  1281. };
  1282. };
  1283.  
  1284. aips-bus@02100000 {
  1285. compatible = "fsl,aips-bus", "simple-bus";
  1286. #address-cells = <0x1>;
  1287. #size-cells = <0x1>;
  1288. reg = <0x2100000 0x100000>;
  1289. ranges;
  1290.  
  1291. caam@2100000 {
  1292. compatible = "fsl,sec-v4.0";
  1293. #address-cells = <0x1>;
  1294. #size-cells = <0x1>;
  1295. reg = <0x2100000 0x40000>;
  1296. ranges = <0x0 0x2100000 0x40000>;
  1297. interrupt-parent = <0x1>;
  1298. clocks = <0x2 0xd5 0x2 0xd6 0x2 0xd7 0x2 0xc4>;
  1299. clock-names = "caam_mem", "caam_aclk", "caam_ipg", "emi_slow";
  1300.  
  1301. jr0@1000 {
  1302. compatible = "fsl,sec-v4.0-job-ring";
  1303. reg = <0x1000 0x1000>;
  1304. interrupt-parent = <0x1>;
  1305. interrupts = <0x0 0x69 0x4>;
  1306. };
  1307.  
  1308. jr1@2000 {
  1309. compatible = "fsl,sec-v4.0-job-ring";
  1310. reg = <0x2000 0x1000>;
  1311. interrupt-parent = <0x1>;
  1312. interrupts = <0x0 0x6a 0x4>;
  1313. };
  1314. };
  1315.  
  1316. aipstz@0217c000 {
  1317. reg = <0x217c000 0x4000>;
  1318. };
  1319.  
  1320. usb@02184000 {
  1321. compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
  1322. reg = <0x2184000 0x200>;
  1323. interrupts = <0x0 0x2b 0x4>;
  1324. clocks = <0x2 0xa2>;
  1325. fsl,usbphy = <0x14>;
  1326. fsl,usbmisc = <0x15 0x0>;
  1327. fsl,anatop = <0x11>;
  1328. status = "okay";
  1329. vbus-supply = <0x16>;
  1330. pinctrl-names = "default";
  1331. pinctrl-0 = <0x17>;
  1332. disable-over-current;
  1333. };
  1334.  
  1335. usb@02184200 {
  1336. compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
  1337. reg = <0x2184200 0x200>;
  1338. interrupts = <0x0 0x28 0x4>;
  1339. clocks = <0x2 0xa2>;
  1340. fsl,usbphy = <0x18>;
  1341. fsl,usbmisc = <0x15 0x1>;
  1342. status = "okay";
  1343. vbus-supply = <0x19>;
  1344. };
  1345.  
  1346. usb@02184400 {
  1347. compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
  1348. reg = <0x2184400 0x200>;
  1349. interrupts = <0x0 0x29 0x4>;
  1350. clocks = <0x2 0xa2>;
  1351. fsl,usbmisc = <0x15 0x2>;
  1352. phy_type = "hsic";
  1353. fsl,usbphy = <0x1a>;
  1354. fsl,anatop = <0x11>;
  1355. status = "disabled";
  1356. };
  1357.  
  1358. usb@02184600 {
  1359. compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
  1360. reg = <0x2184600 0x200>;
  1361. interrupts = <0x0 0x2a 0x4>;
  1362. clocks = <0x2 0xa2>;
  1363. fsl,usbmisc = <0x15 0x3>;
  1364. phy_type = "hsic";
  1365. fsl,usbphy = <0x1b>;
  1366. fsl,anatop = <0x11>;
  1367. status = "disabled";
  1368. };
  1369.  
  1370. usbmisc@02184800 {
  1371. #index-cells = <0x1>;
  1372. compatible = "fsl,imx6q-usbmisc";
  1373. reg = <0x2184800 0x200>;
  1374. clocks = <0x2 0xa2>;
  1375. linux,phandle = <0x15>;
  1376. phandle = <0x15>;
  1377. };
  1378.  
  1379. ethernet@02188000 {
  1380. compatible = "fsl,imx6q-fec";
  1381. reg = <0x2188000 0x4000>;
  1382. interrupts = <0x0 0x76 0x4 0x0 0x77 0x4>;
  1383. clocks = <0x2 0x75 0x2 0x75 0x2 0xbe>;
  1384. clock-names = "ipg", "ahb", "ptp";
  1385. status = "okay";
  1386. pinctrl-names = "default";
  1387. pinctrl-0 = <0x1c>;
  1388. phy-mode = "rgmii";
  1389. };
  1390.  
  1391. mlb@0218c000 {
  1392. compatible = "fsl,imx6q-mlb150";
  1393. reg = <0x218c000 0x4000>;
  1394. interrupts = <0x0 0x35 0x4 0x0 0x75 0x4 0x0 0x7e 0x4>;
  1395. clocks = <0x2 0x8b 0x2 0xaf>;
  1396. clock-names = "mlb", "pll8_mlb";
  1397. iram = <0xb>;
  1398. status = "disabled";
  1399. };
  1400.  
  1401. usdhc@02190000 {
  1402. compatible = "fsl,imx6q-usdhc";
  1403. reg = <0x2190000 0x4000>;
  1404. interrupts = <0x0 0x16 0x4>;
  1405. clocks = <0x2 0xa3 0x2 0xa3 0x2 0xa3>;
  1406. clock-names = "ipg", "ahb", "per";
  1407. bus-width = <0x4>;
  1408. status = "okay";
  1409. pinctrl-names = "default";
  1410. pinctrl-0 = <0x1d>;
  1411. non-removable;
  1412. no-1-8-v;
  1413. };
  1414.  
  1415. usdhc@02194000 {
  1416. compatible = "fsl,imx6q-usdhc";
  1417. reg = <0x2194000 0x4000>;
  1418. interrupts = <0x0 0x17 0x4>;
  1419. clocks = <0x2 0xa4 0x2 0xa4 0x2 0xa4>;
  1420. clock-names = "ipg", "ahb", "per";
  1421. bus-width = <0x4>;
  1422. status = "okay";
  1423. pinctrl-names = "default";
  1424. pinctrl-0 = <0x1e>;
  1425. cd-gpios = <0x1f 0x14 0x0>;
  1426. no-1-8-v;
  1427. };
  1428.  
  1429. usdhc@02198000 {
  1430. compatible = "fsl,imx6q-usdhc";
  1431. reg = <0x2198000 0x4000>;
  1432. interrupts = <0x0 0x18 0x4>;
  1433. clocks = <0x2 0xa5 0x2 0xa5 0x2 0xa5>;
  1434. clock-names = "ipg", "ahb", "per";
  1435. bus-width = <0x8>;
  1436. status = "okay";
  1437. pinctrl-names = "default";
  1438. pinctrl-0 = <0x20>;
  1439. pinctrl-assert-gpios = <0x21 0x8 0x0>;
  1440. non-removable;
  1441. };
  1442.  
  1443. usdhc@0219c000 {
  1444. compatible = "fsl,imx6q-usdhc";
  1445. reg = <0x219c000 0x4000>;
  1446. interrupts = <0x0 0x19 0x4>;
  1447. clocks = <0x2 0xa6 0x2 0xa6 0x2 0xa6>;
  1448. clock-names = "ipg", "ahb", "per";
  1449. bus-width = <0x4>;
  1450. status = "disabled";
  1451. };
  1452.  
  1453. i2c@021a0000 {
  1454. #address-cells = <0x1>;
  1455. #size-cells = <0x0>;
  1456. compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
  1457. reg = <0x21a0000 0x4000>;
  1458. interrupts = <0x0 0x24 0x4>;
  1459. clocks = <0x2 0x7d>;
  1460. status = "okay";
  1461. pinctrl-names = "default";
  1462. pinctrl-0 = <0x22>;
  1463. clock-frequency = <0x186a0>;
  1464.  
  1465. tlv320aic3107@18 {
  1466. compatible = "ti,tlv320aic3107";
  1467. clock-frequency = <0xb71b00>;
  1468. reg = <0x18>;
  1469. linux,phandle = <0x35>;
  1470. phandle = <0x35>;
  1471. };
  1472.  
  1473. adv7180@20 {
  1474. compatible = "adv,adv7180";
  1475. reg = <0x20>;
  1476. pinctrl-names = "default";
  1477. pinctrl-0 = <0x23>;
  1478. clocks = <0x2 0xc9>;
  1479. clock-names = "csi_mclk";
  1480. DOVDD-supply = <0x24>;
  1481. AVDD-supply = <0x24>;
  1482. DVDD-supply = <0x24>;
  1483. PVDD-supply = <0x24>;
  1484. csi_id = <0x0>;
  1485. mclk = <0x16e3600>;
  1486. mclk_source = <0x0>;
  1487. cvbs = <0x1>;
  1488. };
  1489.  
  1490. encoder@20 {
  1491. compatible = "bustec,bt125_exp";
  1492. gpio-controller;
  1493. #gpio-cells = <0x2>;
  1494. interrupt-parent = <0x5>;
  1495. interrupts = <0x4 0x2>;
  1496. reg = <0x20 0x1>;
  1497. };
  1498.  
  1499. bustec@3a {
  1500. compatible = "bustec,bt125";
  1501. #gpio-cells = <0x2>;
  1502. interrupt-parent = <0x5>;
  1503. interrupts = <0x4 0x2>;
  1504. reg = <0x3a 0x1>;
  1505. };
  1506.  
  1507. sgtl5000@0a {
  1508. compatible = "fsl,sgtl5000";
  1509. reg = <0xa>;
  1510. clocks = <0x2 0xc9>;
  1511. VDDA-supply = <0x25>;
  1512. VDDIO-supply = <0x24>;
  1513. VDDD-supply = <0x26>;
  1514. linux,phandle = <0x36>;
  1515. phandle = <0x36>;
  1516. };
  1517.  
  1518. adp5589@34 {
  1519. compatible = "bustec,bt125_adp5589";
  1520. #gpio-cells = <0x2>;
  1521. reg = <0x34 0x1>;
  1522. led_init = <0xaf>;
  1523. };
  1524.  
  1525. eeprom@57 {
  1526. compatible = "at24,24c64";
  1527. reg = <0x57>;
  1528. };
  1529.  
  1530. temperature@4f {
  1531. compatible = "national,lm75";
  1532. reg = <0x4f>;
  1533. };
  1534.  
  1535. 1w@18 {
  1536. compatible = "dallas,ds2482";
  1537. reg = <0x18>;
  1538. };
  1539.  
  1540. akcelerometr@53 {
  1541. compatible = "bustec,bt125_adx";
  1542. #gpio-cells = <0x2>;
  1543. interrupt-parent = <0x5>;
  1544. interrupts = <0x4 0x2>;
  1545. reg = <0x53>;
  1546. };
  1547. };
  1548.  
  1549. i2c@021a4000 {
  1550. #address-cells = <0x1>;
  1551. #size-cells = <0x0>;
  1552. compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
  1553. reg = <0x21a4000 0x4000>;
  1554. interrupts = <0x0 0x25 0x4>;
  1555. clocks = <0x2 0x7e>;
  1556. status = "okay";
  1557. pinctrl-names = "default";
  1558. pinctrl-0 = <0x27>;
  1559. clock-frequency = <0x186a0>;
  1560. linux,phandle = <0x2c>;
  1561. phandle = <0x2c>;
  1562.  
  1563. eeprom@54 {
  1564. compatible = "at,24c04";
  1565. pagesize = <0x10>;
  1566. reg = <0x54>;
  1567. };
  1568.  
  1569. tsp@58 {
  1570. compatible = "da9063";
  1571. device_type = "mfd";
  1572. pinctrl-names = "default";
  1573. pinctrl-0 = <0x28>;
  1574. reg = <0x58>;
  1575. interrupt-parent = <0x21>;
  1576. interrupts = <0xc 0x8>;
  1577. off-sequence = <0x1900d4 0xe0001>;
  1578. sleep-sequence = <0x1b009e 0xd0020 0x11700c0 0xb0030 0x1140089 0x200061 0x210061>;
  1579. wake-sequence = <0x11700cc>;
  1580.  
  1581. rtc {
  1582. compatible = "dialog,da9063-rtc";
  1583. };
  1584.  
  1585. battery {
  1586. compatible = "dialog,da9063-battery";
  1587. charging-uA = <0x1770>;
  1588. charging-mV = <0xc1c>;
  1589. };
  1590.  
  1591. regulators {
  1592.  
  1593. bcore1 {
  1594. regulator-name = "bcore1";
  1595. regulator-always-on = <0x1>;
  1596. regulator-min-microvolt = <0x493e0>;
  1597. regulator-max-microvolt = <0x325aa0>;
  1598. };
  1599.  
  1600. bcore2 {
  1601. regulator-name = "bcore2";
  1602. regulator-always-on = <0x1>;
  1603. regulator-min-microvolt = <0x15aae0>;
  1604. regulator-max-microvolt = <0x15aae0>;
  1605. };
  1606.  
  1607. bpro {
  1608. regulator-name = "bpro";
  1609. regulator-always-on = <0x1>;
  1610. regulator-min-microvolt = <0x14c080>;
  1611. regulator-max-microvolt = <0x14c080>;
  1612. };
  1613.  
  1614. bperi {
  1615. regulator-name = "bperi";
  1616. regulator-always-on = <0x1>;
  1617. regulator-min-microvolt = <0x493e0>;
  1618. regulator-max-microvolt = <0x325aa0>;
  1619. };
  1620.  
  1621. bmem {
  1622. regulator-name = "bmem";
  1623. regulator-always-on = <0x1>;
  1624. regulator-min-microvolt = <0x14c080>;
  1625. regulator-max-microvolt = <0x14c080>;
  1626. };
  1627.  
  1628. ldo2 {
  1629. regulator-name = "ldo2";
  1630. regulator-always-on = <0x1>;
  1631. regulator-min-microvolt = <0x493e0>;
  1632. regulator-max-microvolt = <0x1b7740>;
  1633. };
  1634.  
  1635. ldo3 {
  1636. regulator-name = "ldo3";
  1637. regulator-always-on = <0x1>;
  1638. regulator-min-microvolt = <0x493e0>;
  1639. regulator-max-microvolt = <0x325aa0>;
  1640. };
  1641.  
  1642. ldo4 {
  1643. regulator-name = "ldo4";
  1644. regulator-always-on = <0x1>;
  1645. regulator-min-microvolt = <0x493e0>;
  1646. regulator-max-microvolt = <0x325aa0>;
  1647. };
  1648.  
  1649. ldo5 {
  1650. regulator-name = "ldo5";
  1651. regulator-always-on = <0x1>;
  1652. regulator-min-microvolt = <0x493e0>;
  1653. regulator-max-microvolt = <0x325aa0>;
  1654. };
  1655.  
  1656. ldo6 {
  1657. regulator-name = "ldo6";
  1658. regulator-always-on = <0x1>;
  1659. regulator-min-microvolt = <0x493e0>;
  1660. regulator-max-microvolt = <0x325aa0>;
  1661. };
  1662.  
  1663. ldo7 {
  1664. regulator-name = "ldo7";
  1665. regulator-always-on = <0x1>;
  1666. regulator-min-microvolt = <0x493e0>;
  1667. regulator-max-microvolt = <0x325aa0>;
  1668. };
  1669.  
  1670. ldo8 {
  1671. regulator-name = "ldo8";
  1672. regulator-always-on = <0x1>;
  1673. regulator-min-microvolt = <0x493e0>;
  1674. regulator-max-microvolt = <0x325aa0>;
  1675. };
  1676.  
  1677. ldo9 {
  1678. regulator-name = "ldo9";
  1679. regulator-always-on = <0x1>;
  1680. regulator-min-microvolt = <0x493e0>;
  1681. regulator-max-microvolt = <0x325aa0>;
  1682. };
  1683.  
  1684. ldo10 {
  1685. regulator-name = "ldo10";
  1686. regulator-always-on = <0x1>;
  1687. regulator-min-microvolt = <0x493e0>;
  1688. regulator-max-microvolt = <0x325aa0>;
  1689. };
  1690.  
  1691. ldo11 {
  1692. regulator-name = "ldo11";
  1693. regulator-always-on = <0x1>;
  1694. regulator-min-microvolt = <0x493e0>;
  1695. regulator-max-microvolt = <0x325aa0>;
  1696. };
  1697.  
  1698. bio {
  1699. regulator-name = "bio";
  1700. regulator-always-on = <0x1>;
  1701. regulator-min-microvolt = <0x124f80>;
  1702. regulator-max-microvolt = <0x124f80>;
  1703. };
  1704. };
  1705. };
  1706. };
  1707.  
  1708. i2c@021a8000 {
  1709. #address-cells = <0x1>;
  1710. #size-cells = <0x0>;
  1711. compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
  1712. reg = <0x21a8000 0x4000>;
  1713. interrupts = <0x0 0x26 0x4>;
  1714. clocks = <0x2 0x7f>;
  1715. status = "disabled";
  1716. };
  1717.  
  1718. romcp@021ac000 {
  1719. reg = <0x21ac000 0x4000>;
  1720. };
  1721.  
  1722. mmdc0-1@021b0000 {
  1723. compatible = "fsl,imx6q-mmdc-combine";
  1724. reg = <0x21b0000 0x8000>;
  1725. };
  1726.  
  1727. mmdc@021b0000 {
  1728. compatible = "fsl,imx6q-mmdc";
  1729. reg = <0x21b0000 0x4000>;
  1730. };
  1731.  
  1732. mmdc@021b4000 {
  1733. reg = <0x21b4000 0x4000>;
  1734. };
  1735.  
  1736. weim@021b8000 {
  1737. compatible = "fsl,imx6q-weim";
  1738. reg = <0x21b8000 0x4000>;
  1739. interrupts = <0x0 0xe 0x4>;
  1740. clocks = <0x2 0xc4>;
  1741. };
  1742.  
  1743. ocotp-ctrl@021bc000 {
  1744. compatible = "syscon";
  1745. reg = <0x21bc000 0x4000>;
  1746. linux,phandle = <0x12>;
  1747. phandle = <0x12>;
  1748. };
  1749.  
  1750. ocotp-fuse@021bc000 {
  1751. compatible = "fsl,imx6q-ocotp";
  1752. reg = <0x21bc000 0x4000>;
  1753. clocks = <0x2 0x80>;
  1754. };
  1755.  
  1756. tzasc@021d0000 {
  1757. reg = <0x21d0000 0x4000>;
  1758. interrupts = <0x0 0x6c 0x4>;
  1759. };
  1760.  
  1761. tzasc@021d4000 {
  1762. reg = <0x21d4000 0x4000>;
  1763. interrupts = <0x0 0x6d 0x4>;
  1764. };
  1765.  
  1766. audmux@021d8000 {
  1767. compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
  1768. reg = <0x21d8000 0x4000>;
  1769. status = "okay";
  1770. pinctrl-names = "default";
  1771. pinctrl-0 = <0x29>;
  1772. };
  1773.  
  1774. mipi_csi@021dc000 {
  1775. compatible = "fsl,imx6q-mipi-csi2";
  1776. reg = <0x21dc000 0x4000>;
  1777. interrupts = <0x0 0x64 0x4 0x0 0x65 0x4>;
  1778. clocks = <0x2 0x8a 0x2 0x35 0x2 0xcc>;
  1779. clock-names = "dphy_clk", "pixel_clk", "cfg_clk";
  1780. status = "disabled";
  1781. };
  1782.  
  1783. vdoa@021e4000 {
  1784. compatible = "fsl,imx6q-vdoa";
  1785. reg = <0x21e4000 0x4000>;
  1786. interrupts = <0x0 0x12 0x4>;
  1787. clocks = <0x2 0xca>;
  1788. iram = <0xb>;
  1789. };
  1790.  
  1791. serial@021e8000 {
  1792. compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
  1793. reg = <0x21e8000 0x4000>;
  1794. interrupts = <0x0 0x1b 0x4>;
  1795. clocks = <0x2 0xa0 0x2 0xa1>;
  1796. clock-names = "ipg", "per";
  1797. dmas = <0x6 0x1b 0x4 0x0 0x6 0x1c 0x4 0x0>;
  1798. dma-names = "rx", "tx";
  1799. status = "okay";
  1800. pinctrl-names = "default";
  1801. pinctrl-0 = <0x2a>;
  1802. };
  1803.  
  1804. serial@021ec000 {
  1805. compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
  1806. reg = <0x21ec000 0x4000>;
  1807. interrupts = <0x0 0x1c 0x4>;
  1808. clocks = <0x2 0xa0 0x2 0xa1>;
  1809. clock-names = "ipg", "per";
  1810. dmas = <0x6 0x1d 0x4 0x0 0x6 0x1e 0x4 0x0>;
  1811. dma-names = "rx", "tx";
  1812. status = "okay";
  1813. pinctrl-names = "default";
  1814. pinctrl-0 = <0x2b>;
  1815. };
  1816.  
  1817. serial@021f0000 {
  1818. compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
  1819. reg = <0x21f0000 0x4000>;
  1820. interrupts = <0x0 0x1d 0x4>;
  1821. clocks = <0x2 0xa0 0x2 0xa1>;
  1822. clock-names = "ipg", "per";
  1823. dmas = <0x6 0x1f 0x4 0x0 0x6 0x20 0x4 0x0>;
  1824. dma-names = "rx", "tx";
  1825. status = "disabled";
  1826. };
  1827.  
  1828. serial@021f4000 {
  1829. compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
  1830. reg = <0x21f4000 0x4000>;
  1831. interrupts = <0x0 0x1e 0x4>;
  1832. clocks = <0x2 0xa0 0x2 0xa1>;
  1833. clock-names = "ipg", "per";
  1834. dmas = <0x6 0x21 0x4 0x0 0x6 0x22 0x4 0x0>;
  1835. dma-names = "rx", "tx";
  1836. status = "disabled";
  1837. };
  1838.  
  1839. mipi@021e0000 {
  1840. compatible = "fsl,imx6dl-mipi-dsi";
  1841. reg = <0x21e0000 0x4000>;
  1842. interrupts = <0x0 0x66 0x4>;
  1843. gpr = <0xf>;
  1844. clocks = <0x2 0x8a 0x2 0xcc>;
  1845. clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
  1846. status = "disabled";
  1847. };
  1848.  
  1849. i2c@021f8000 {
  1850. #address-cells = <0x1>;
  1851. #size-cells = <0x0>;
  1852. compatible = "fsl,imx1-i2c";
  1853. reg = <0x21f8000 0x4000>;
  1854. interrupts = <0x0 0x23 0x4>;
  1855. status = "disabled";
  1856. clocks = <0x2 0x74>;
  1857. };
  1858.  
  1859. i2cmux {
  1860. compatible = "i2c-mux-gpio";
  1861. #address-cells = <0x1>;
  1862. #size-cells = <0x0>;
  1863. mux-gpios = <0x5 0x7 0x0>;
  1864. i2c-parent = <0x2c>;
  1865. idle-state = <0x0>;
  1866.  
  1867. i2c2@0 {
  1868. #address-cells = <0x1>;
  1869. #size-cells = <0x0>;
  1870. reg = <0x0>;
  1871. };
  1872.  
  1873. i2c2@1 {
  1874. #address-cells = <0x1>;
  1875. #size-cells = <0x0>;
  1876. reg = <0x1>;
  1877. };
  1878. };
  1879. };
  1880.  
  1881. ipu@02400000 {
  1882. compatible = "fsl,imx6q-ipu";
  1883. reg = <0x2400000 0x400000>;
  1884. interrupts = <0x0 0x6 0x4 0x0 0x5 0x4>;
  1885. clocks = <0x2 0x82 0x2 0x83 0x2 0x84 0x2 0x27 0x2 0x28 0x2 0x87 0x2 0x88>;
  1886. clock-names = "bus", "di0", "di1", "di0_sel", "di1_sel", "ldb_di0", "ldb_di1";
  1887. resets = <0xc 0x2>;
  1888. bypass_reset = <0x0>;
  1889. };
  1890.  
  1891. busfreq {
  1892. compatible = "fsl,imx6_busfreq";
  1893. clocks = <0x2 0xab 0x2 0x6 0x2 0xb 0x2 0x68 0x2 0xac 0x2 0x3a 0x2 0x12 0x2 0x3c 0x2 0x14 0x2 0x3 0x2 0x16 0x2 0x8>;
  1894. clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_sel", "pll3_pfd1_540m";
  1895. interrupts = <0x0 0x6b 0x4 0x0 0x70 0x4>;
  1896. interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
  1897. fsl,max_ddr_freq = <0x17d78400>;
  1898. };
  1899.  
  1900. gpu@00130000 {
  1901. compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
  1902. reg = <0x130000 0x4000 0x134000 0x4000 0x0 0x0>;
  1903. reg-names = "iobase_3d", "iobase_2d", "phys_baseaddr";
  1904. interrupts = <0x0 0x9 0x4 0x0 0xa 0x4>;
  1905. interrupt-names = "irq_3d", "irq_2d";
  1906. clocks = <0x2 0x8f 0x2 0x1b 0x2 0x79 0x2 0x7a 0x2 0x0>;
  1907. clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk", "gpu2d_clk", "gpu3d_clk", "gpu3d_shader_clk";
  1908. resets = <0xc 0x0 0xc 0x3>;
  1909. reset-names = "gpu3d", "gpu2d";
  1910. pu-supply = <0xd>;
  1911. };
  1912.  
  1913. sram@00900000 {
  1914. compatible = "mmio-sram";
  1915. reg = <0x904000 0x1c000>;
  1916. clocks = <0x2 0x8e>;
  1917. linux,phandle = <0xb>;
  1918. phandle = <0xb>;
  1919. };
  1920.  
  1921. hdmi_core@00120000 {
  1922. compatible = "fsl,imx6dl-hdmi-core";
  1923. reg = <0x120000 0x9000>;
  1924. clocks = <0x2 0x7c 0x2 0x7b>;
  1925. clock-names = "hdmi_isfr", "hdmi_iahb";
  1926. status = "disabled";
  1927. };
  1928.  
  1929. hdmi_video@020e0000 {
  1930. compatible = "fsl,imx6dl-hdmi-video";
  1931. reg = <0x20e0000 0x1000>;
  1932. reg-names = "hdmi_gpr";
  1933. interrupts = <0x0 0x73 0x4>;
  1934. clocks = <0x2 0x7c 0x2 0x7b>;
  1935. clock-names = "hdmi_isfr", "hdmi_iahb";
  1936. status = "disabled";
  1937. };
  1938.  
  1939. hdmi_audio@00120000 {
  1940. compatible = "fsl,imx6dl-hdmi-audio";
  1941. clocks = <0x2 0x7c 0x2 0x7b>;
  1942. clock-names = "hdmi_isfr", "hdmi_iahb";
  1943. dmas = <0x6 0x2 0x16 0x0>;
  1944. dma-names = "tx";
  1945. status = "disabled";
  1946. };
  1947.  
  1948. hdmi_cec@00120000 {
  1949. compatible = "fsl,imx6dl-hdmi-cec";
  1950. interrupts = <0x0 0x73 0x4>;
  1951. status = "disabled";
  1952. };
  1953. };
  1954.  
  1955. cpus {
  1956. #address-cells = <0x1>;
  1957. #size-cells = <0x0>;
  1958.  
  1959. cpu@0 {
  1960. compatible = "arm,cortex-a9";
  1961. device_type = "cpu";
  1962. reg = <0x0>;
  1963. next-level-cache = <0x2d>;
  1964. operating-points = <0xf32a0 0x137478 0xc15c0 0x11edd8 0x60ae0 0x106738>;
  1965. fsl,soc-operating-points = <0xf32a0 0x11edd8 0xc15c0 0x11edd8 0x60ae0 0x11edd8>;
  1966. clock-latency = <0xee6c>;
  1967. clocks = <0x2 0x68 0x2 0x6 0x2 0x10 0x2 0x11 0x2 0xaa>;
  1968. clock-names = "arm", "pll2_pfd2_396m", "step", "pll1_sw", "pll1_sys";
  1969. arm-supply = <0x2e>;
  1970. pu-supply = <0xd>;
  1971. soc-supply = <0x2f>;
  1972. };
  1973.  
  1974. cpu@1 {
  1975. compatible = "arm,cortex-a9";
  1976. device_type = "cpu";
  1977. reg = <0x1>;
  1978. next-level-cache = <0x2d>;
  1979. };
  1980. };
  1981.  
  1982. regulators {
  1983. compatible = "simple-bus";
  1984.  
  1985. usb_otg_vbus {
  1986. compatible = "regulator-fixed";
  1987. regulator-name = "usb_otg_vbus";
  1988. regulator-min-microvolt = <0x4c4b40>;
  1989. regulator-max-microvolt = <0x4c4b40>;
  1990. gpio = <0x1f 0xf 0x0>;
  1991. enable-active-high;
  1992. linux,phandle = <0x16>;
  1993. phandle = <0x16>;
  1994. };
  1995.  
  1996. usb_h1_vbus {
  1997. compatible = "regulator-fixed";
  1998. regulator-name = "usb_h1_vbus";
  1999. regulator-min-microvolt = <0x4c4b40>;
  2000. regulator-max-microvolt = <0x4c4b40>;
  2001. gpio = <0x5 0x0 0x0>;
  2002. enable-active-high;
  2003. linux,phandle = <0x19>;
  2004. phandle = <0x19>;
  2005. };
  2006.  
  2007. reg_aud_iovdd {
  2008. compatible = "regulator-fixed";
  2009. regulator-name = "IOVDD";
  2010. regulator-min-microvolt = <0x1b7740>;
  2011. regulator-max-microvolt = <0x1b7740>;
  2012. regulator-always-on;
  2013. linux,phandle = <0x26>;
  2014. phandle = <0x26>;
  2015. };
  2016.  
  2017. reg_aud_dvdd {
  2018. compatible = "regulator-fixed";
  2019. regulator-name = "DVDD";
  2020. regulator-min-microvolt = <0x1b7740>;
  2021. regulator-max-microvolt = <0x1b7740>;
  2022. regulator-always-on;
  2023. };
  2024.  
  2025. reg_aud_avdd {
  2026. compatible = "regulator-fixed";
  2027. regulator-name = "AVDD";
  2028. regulator-min-microvolt = <0x325aa0>;
  2029. regulator-max-microvolt = <0x325aa0>;
  2030. regulator-always-on;
  2031. };
  2032.  
  2033. reg_aud_drvdd {
  2034. compatible = "regulator-fixed";
  2035. regulator-name = "DRVDD";
  2036. regulator-min-microvolt = <0x325aa0>;
  2037. regulator-max-microvolt = <0x325aa0>;
  2038. regulator-always-on;
  2039. };
  2040.  
  2041. 3p3v {
  2042. compatible = "regulator-fixed";
  2043. regulator-name = "3P3V";
  2044. regulator-min-microvolt = <0x325aa0>;
  2045. regulator-max-microvolt = <0x325aa0>;
  2046. regulator-always-on;
  2047. linux,phandle = <0x24>;
  2048. phandle = <0x24>;
  2049. };
  2050. };
  2051.  
  2052. leds {
  2053. compatible = "gpio-leds";
  2054. pinctrl-names = "default";
  2055. pinctrl-0 = <0x30>;
  2056.  
  2057. led@1 {
  2058. label = "debug-led-1";
  2059. gpios = <0x5 0x18 0x1>;
  2060. linux,default-trigger = "heartbeat";
  2061. default-state = "off";
  2062. };
  2063.  
  2064. led@2 {
  2065. label = "debug-led-2";
  2066. gpios = <0x31 0x1e 0x1>;
  2067. linux,default-trigger = "mmc0";
  2068. default-state = "off";
  2069. };
  2070.  
  2071. led@3 {
  2072. label = "debug-led-3";
  2073. gpios = <0x5 0x19 0x1>;
  2074. linux,default-trigger = "nand-disk";
  2075. default-state = "off";
  2076. };
  2077. };
  2078.  
  2079. lcd_power_en {
  2080. gpios = <0x31 0x1f 0x0>;
  2081. };
  2082.  
  2083. lvds_cabc_ctrl {
  2084. lvds0-gpios = <0x32 0x10 0x0>;
  2085. };
  2086.  
  2087. latches {
  2088. compatible = [00];
  2089. pinctrl-names = "default";
  2090. u0405-en-gpio = <0x33 0x6 0x1>;
  2091. };
  2092.  
  2093. sound {
  2094. compatible = "fsl,imx-audio-tlv320aic3107";
  2095. model = "imx-tlv320aic3107";
  2096. ssi-controller = <0x34>;
  2097. audio-codec = <0x35>;
  2098. mux-int-port = <0x1>;
  2099. mux-ext-port = <0x3>;
  2100. audio-routing = "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", "Headphone Jack", "HP_OUT";
  2101. };
  2102.  
  2103. v4l2_cap_0 {
  2104. compatible = "fsl,imx6q-v4l2-capture";
  2105. ipu_id = <0x0>;
  2106. csi_id = <0x0>;
  2107. mclk_source = <0x0>;
  2108. status = "okay";
  2109. };
  2110.  
  2111. v4l2_out {
  2112. compatible = "fsl,mxc_v4l2_output";
  2113. status = "okay";
  2114. };
  2115.  
  2116. fb@0 {
  2117. compatible = "fsl,mxc_sdc_fb";
  2118. disp_dev = "ldb";
  2119. interface_pix_fmt = "RGB24";
  2120. mode_str = "LDB-WVGA";
  2121. default_bpp = <0x20>;
  2122. int_clk = <0x0>;
  2123. late_init = <0x0>;
  2124. status = "okay";
  2125. };
  2126.  
  2127. sound2 {
  2128. compatible = "fsl,imx6-wandboard-sgtl5000", "fsl,imx-audio-sgtl5000";
  2129. model = "imx6-wandboard-sgtl5000";
  2130. ssi-controller = <0x34>;
  2131. audio-codec = <0x36>;
  2132. audio-routing = "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", "LINE_IN", "Line In Jack", "Headphone Jack", "HP_OUT", "Ext Spk", "LINE_OUT";
  2133. mux-int-port = <0x1>;
  2134. mux-ext-port = <0x3>;
  2135. };
  2136.  
  2137. 2p5v {
  2138. compatible = "regulator-fixed";
  2139. regulator-name = "2P5V";
  2140. regulator-min-microvolt = <0x2625a0>;
  2141. regulator-max-microvolt = <0x2625a0>;
  2142. regulator-always-on;
  2143. linux,phandle = <0x25>;
  2144. phandle = <0x25>;
  2145. };
  2146.  
  2147. buzzer {
  2148. compatible = "pwm-beeper";
  2149. pwms = <0x37 0x0 0xf4240 0x0>;
  2150. pinctrl-names = "default";
  2151. };
  2152. };
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