library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
--50MHz clk, 2.5kHz f_pwm, 44% duty cycle und offset um 25%
--50MHz/(2.5/1000)MHz=20000 mal zaehlen = x"4E20"
--25%=20000*0.25=5000 = x"1388"
--44% high: 20000*0.44=8800 = x"2260"
--56% low:  20000*0.56=11200 = x"2BC0"
architecture behavior of pwm is
    signal pout: std_logic:='0';
begin

    p1: process(CLK)
        variable cnt: std_logic_vector(15 downto 0):=x"3A98";--beginnt bei 15000=x"3A98"
        variable offset_flag: std_logic:='1';
    begin
        if(rising_edge(CLK)) then
                if(cnt=x"4E1F") then
                    cnt:=x"0000";
                    pout<='1';
                else
                    cnt:=cnt+1;
                end if;

                if(cnt=x"2260") then
                    pout<='0';
                end if;
        end if;
    end process;

    O<=pout;

end behavior;