clock_3

module divisor_3(clk,clk_out);

 input clk;
 output reg clk_out=0;
 reg [1:0] Count;
 reg [1:0] a=0;

 always@(*)begin
 if (Count<2'b10)
  a=Count+1;
 else
 a=0;
 end


 always@(posedge clk)begin
  Count<=a;
 end

 always@(posedge clk)begin
  if (Count==2'b10)
   clk_out<=~clk_out;
  else
   clk_out<=clk_out;
  end



endmodule