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- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use ieee.std_logic_unsigned.all;
- entity Counter_24 is
- Port ( CLK : in STD_LOGIC;
- En : in STD_LOGIC;
- Rst : in STD_LOGIC;
- Cout : out STD_LOGIC;
- Fout : out STD_LOGIC_VECTOR (4 downto 0));
- end Counter_24;
- architecture Behavioral of Counter_24 is
- signal time : std_logic_vector(4 downto 0) := "00000";
- begin
- TT:process(CLK,Rst,En)
- Begin
- if (CLK='1' and CLK'event) then
- if (Rst = '1') then
- time <= "00000";
- Cout <= '0';
- else
- if (En = '1') then
- if (time < "10111") then
- time <= time+1;
- if (time = "10110") then
- Cout <= '1';
- else
- Cout <= '0';
- End if;
- else
- time <= "00000";
- Cout <= '0';
- End if;
- End if;
- End if;
- End if;
- End process;
- Fout <= time;
- end Behavioral;
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